From: Simi Pallipurath <simi.pallipurath@arm.com>
Date: Tue, 6 Mar 2018 15:21:19 +0000 (+0000)
Subject: [ARM]Decoding MSR with unpredictable destination register causes an assert
X-Git-Tag: llvmorg-7.0.0-rc1~11316
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=75c6bfeac9480c6f2877522f064e71dd4c43a6e9;p=platform%2Fupstream%2Fllvm.git

[ARM]Decoding MSR with unpredictable destination register causes an assert

This patch handling:

    Enable parsing of raw encodings of system registers .
    Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
    Disassemble msr/mrs with unpredictable sysregs as SoftFail.
    Fix regression due to SoftFailing some encodings.

Patch by Chris Ryder

Differential revision:https://reviews.llvm.org/D43374

llvm-svn: 326803
---

diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index cbbbdc0..3ec619f 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -4238,6 +4238,18 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   SMLoc S = Parser.getTok().getLoc();
   const AsmToken &Tok = Parser.getTok();
+
+  if (Tok.is(AsmToken::Integer)) {
+    int64_t Val = Tok.getIntVal();
+    if (Val > 255 || Val < 0) {
+      return MatchOperand_NoMatch;
+    }
+    unsigned SYSmvalue = Val & 0xFF;
+    Parser.Lex(); 
+    Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
+    return MatchOperand_Success;
+  }
+
   if (!Tok.is(AsmToken::Identifier))
     return MatchOperand_NoMatch;
   StringRef Mask = Tok.getString();
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index f9a0a74..3ffa702 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -4149,7 +4149,6 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
     case 0x8a: // msplim_ns
     case 0x8b: // psplim_ns
     case 0x91: // basepri_ns
-    case 0x92: // basepri_max_ns
     case 0x93: // faultmask_ns
       if (!(FeatureBits[ARM::HasV8MMainlineOps]))
         return MCDisassembler::Fail;
@@ -4165,7 +4164,9 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
         return MCDisassembler::Fail;
       break;
     default:
-      return MCDisassembler::Fail;
+      // Architecturally defined as unpredictable
+      S = MCDisassembler::SoftFail;
+      break;
     }
 
     if (Inst.getOpcode() == ARM::t2MSR_M) {
diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index 4fc67a4..507e3f1 100644
--- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -825,7 +825,8 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
       return;
     }
 
-    llvm_unreachable("Unexpected mask value!");
+    O << SYSm; 
+
     return;
   }
 
diff --git a/llvm/test/MC/ARM/thumbv8m.s b/llvm/test/MC/ARM/thumbv8m.s
index 5ff58ccc..88ca22f 100644
--- a/llvm/test/MC/ARM/thumbv8m.s
+++ b/llvm/test/MC/ARM/thumbv8m.s
@@ -225,6 +225,12 @@ MSR FAULTMASK_NS, r14
 // CHECK-MAINLINE: msr faultmask_ns, lr  @ encoding: [0x8e,0xf3,0x93,0x88]
 // UNDEF-BASELINE: error: invalid operand for instruction
 
+// Unpredictable SYSm's
+MRS r8, 146
+// CHECK: mrs r8, 146 @ encoding: [0xef,0xf3,0x92,0x88]
+MSR 146, r8
+// CHECK: msr 146, r8 @ encoding: [0x88,0xf3,0x92,0x80]
+
 // Invalid operand tests
 // UNDEF: error: too many operands for instruction
 // UNDEF:     sg #0
diff --git a/llvm/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt b/llvm/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt
index f40c721..6c6cc010 100644
--- a/llvm/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt
+++ b/llvm/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt
@@ -1,12 +1,12 @@
-# RUN: not llvm-mc -disassemble %s -triple=thumbv7em 2>&1 | FileCheck %s
-# RUN: not llvm-mc -disassemble %s -triple=thumbv7m 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
+# RUN: llvm-mc -disassemble %s -triple=thumbv7em 2>&1 | FileCheck %s
+# RUN: llvm-mc -disassemble %s -triple=thumbv7m 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
 
 #------------------------------------------------------------------------------
 # Undefined encodings for mrs
 #------------------------------------------------------------------------------
 
 # invalid SYSm
-# CHECK: warning: invalid instruction encoding
+# CHECK: warning: potentially undefined instruction encoding
 # CHECK-NEXT: [0xef 0xf3 0x80 0x80]
 [0xef 0xf3 0x80 0x80]
 
@@ -30,6 +30,6 @@
 [0x80 0xf3 0x00 0x84]
 
 # invalid SYSm
-# CHECK: warning: invalid instruction encoding
+# CHECK: warning: potentially undefined instruction encoding
 # CHECK-NEXT: [0x80 0xf3 0x80 0x88]
 [0x80 0xf3 0x80 0x88]