From: Robert Richter Date: Tue, 7 Aug 2012 17:43:15 +0000 (+0200) Subject: perf list: Update documentation about raw event setup X-Git-Tag: v3.8-rc1~60^2~73^2~68 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=75bc5ca89827fe3f2399321b2920a30bcf658049;p=platform%2Fupstream%2Fkernel-adaptation-pc.git perf list: Update documentation about raw event setup It was missing that only certain bit fields are passed to the config value which confused users. Updating it. Signed-off-by: Robert Richter Cc: Ingo Molnar Link: http://lkml.kernel.org/r/1344361396-7237-6-git-send-email-robert.richter@amd.com Signed-off-by: Arnaldo Carvalho de Melo --- diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt index ddc2252..232be51 100644 --- a/tools/perf/Documentation/perf-list.txt +++ b/tools/perf/Documentation/perf-list.txt @@ -15,6 +15,7 @@ DESCRIPTION This command displays the symbolic event types which can be selected in the various perf commands with the -e option. +[[EVENT_MODIFIERS]] EVENT MODIFIERS --------------- @@ -44,6 +45,11 @@ layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Softwar of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). +Note: Only the following bit fields can be set in x86 counter +registers: event, umask, edge, inv, cmask. Esp. guest/host only and +OS/user mode flags must be setup using <>. + Example: If the Intel docs for a QM720 Core i7 describe an event as: