From: Andy Chiu <andy.chiu@sifive.com>
Date: Tue, 27 Jun 2023 01:55:54 +0000 (+0000)
Subject: riscv: vector: clear V-reg in the first-use trap
X-Git-Tag: v6.6.7~2398^2~12
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=75b59f2a90aa7ccac62e3dcb680dfb967b341431;p=platform%2Fkernel%2Flinux-starfive.git

riscv: vector: clear V-reg in the first-use trap

If there is no context switch happens after we enable V for a process,
then we return to user space with whatever left on the CPU's V registers
accessible to the process. The leaked data could belong to another
process's V-context saved from last context switch, impacting process's
confidentiality on the system.

To prevent this from happening, we clear V registers by restoring
zero'd V context after turining on V.

Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Link: https://lore.kernel.org/r/20230627015556.12329-2-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---

diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index f9c8e19..8d92fb6 100644
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -167,6 +167,7 @@ bool riscv_v_first_use_handler(struct pt_regs *regs)
 		return true;
 	}
 	riscv_v_vstate_on(regs);
+	riscv_v_vstate_restore(current, regs);
 	return true;
 }