From: Pali Rohár Date: Fri, 27 Aug 2021 12:14:43 +0000 (+0200) Subject: arm: a37xx: pci: Disable returning CRS response X-Git-Tag: v2021.10~28^2~7 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=758262bc266aa65cfbfd74033c3ac1e4e67c92ec;p=platform%2Fkernel%2Fu-boot.git arm: a37xx: pci: Disable returning CRS response There was mistake in commit 4cd61c43fd51 ("arm: a37xx: pci: Fix handling PIO config error responses"). U-Boot does not support handling of CRS return value for PCI_VENDOR_ID config read request and also does not set CRSSVE bit. Therefore disable returning CRS response for now. Signed-off-by: Pali Rohár Fixes: 4cd61c43fd51 ("arm: a37xx: pci: Fix handling PIO config error responses") Reviewed-by: Stefan Roese --- diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 815b261..d3ef8f2 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -358,7 +358,18 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } - allow_crs = (offset == PCI_VENDOR_ID) && (size == 4); + /* + * Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to + * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and + * only when CRSSVE bit in Root Port PCIe device is enabled. In all + * other error PCIe Root Complex must return all-ones. + * Aardvark HW does not have Root Port PCIe device and U-Boot does not + * implement emulation of this device. + * U-Boot currently does not support handling of CRS return value for + * PCI_VENDOR_ID config read request and also does not set CRSSVE bit. + * Therefore disable returning CRS response for now. + */ + allow_crs = false; if (advk_readl(pcie, PIO_START)) { dev_err(pcie->dev,