From: Pratyush Yadav
Date: Tue, 22 Dec 2020 18:44:22 +0000 (+0530)
Subject: spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1
X-Git-Tag: v5.15~939^2~100^2~48
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7512eaf54190e4cc9247f18439c008d44b15022c;p=platform%2Fkernel%2Flinux-starfive.git
spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1
SPI MEM deals with dummy bytes but the controller deals with dummy
cycles. Multiplying bytes by 8 is correct if the dummy phase uses 1S
mode since 1 byte will be sent in 8 cycles. But if the dummy phase uses
4S mode then 1 byte will be sent in 2 cycles.
To correctly translate dummy bytes to dummy cycles, the dummy buswidth
also needs to be taken into account. Divide 8 by the buswidth to get the
correct multiplier for getting the number of cycles.
Signed-off-by: Pratyush Yadav
Link: https://lore.kernel.org/r/20201222184425.7028-5-p.yadav@ti.com
Signed-off-by: Mark Brown
---
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 6a77801..376abef 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -294,7 +294,7 @@ static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op)
{
unsigned int dummy_clk;
- dummy_clk = op->dummy.nbytes * 8;
+ dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
return dummy_clk;
}