From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Wed, 30 Nov 2022 15:42:25 +0000 (+0000)
Subject: [X86] Remove unnecessary XADD*rr overrides from bdver2 model
X-Git-Tag: upstream/17.0.6~25740
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=74c0f57d0b3f9fccf8f9c91290de45201687424b;p=platform%2Fupstream%2Fllvm.git

[X86] Remove unnecessary XADD*rr overrides from bdver2 model

Reported by D138359 - the overrides matched the base class schedule definition
---

diff --git a/llvm/lib/Target/X86/X86ScheduleBdVer2.td b/llvm/lib/Target/X86/X86ScheduleBdVer2.td
index 942ef59..c8dafcd 100644
--- a/llvm/lib/Target/X86/X86ScheduleBdVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBdVer2.td
@@ -411,13 +411,6 @@ def PdWriteCMPXCHG16B : SchedWriteRes<[PdEX1]> {
 }
 def : InstRW<[PdWriteCMPXCHG16B], (instrs CMPXCHG16B)>;
 
-def PdWriteXADD : SchedWriteRes<[PdEX1]> {
-  let Latency = 1;
-  let ResourceCycles = [1];
-  let NumMicroOps = 2;
-}
-def : InstRW<[PdWriteXADD], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr)>;
-
 def PdWriteXADDm : SchedWriteRes<[PdEX1]> {
   let Latency = 6;
   let ResourceCycles = [20];