From: Homer Hsing <homer.xing@intel.com>
Date: Thu, 20 Sep 2012 05:09:15 +0000 (+0800)
Subject: Fix field length of JIP for one-offset-branch in Gen6
X-Git-Tag: intel-gpu-tools-1.4~594
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=741008e0503df0a0626d27da99a30aac0c880c29;p=profile%2Fextras%2Fintel-gpu-tools.git

Fix field length of JIP for one-offset-branch in Gen6

Such JIP has 25 bits length in Gen6.
---

diff --git a/assembler/src/brw_structs.h b/assembler/src/brw_structs.h
index 9a0c805..b60f8b7 100644
--- a/assembler/src/brw_structs.h
+++ b/assembler/src/brw_structs.h
@@ -1311,7 +1311,10 @@ struct brw_instruction
       {
 	 GLint JIP:16; /* bspec: both the JIP and UIP are signed 16-bit numbers */
 	 GLint UIP:16;
-      } branch; /* for branch instructions: brc, brd, if, else, endif, while, break, cont, call, ret, halt, ... */
+      } branch_2_offset; /* for Gen6, Gen7 2-offsets branch instructions */
+
+      GLint JIP; /* for Gen6, Gen7 1-offset branch instructions 
+                    Gen6 uses low 25 bits. Gen7 uses low 16 bits. */
 
       struct {
 	 GLuint function:4;
diff --git a/assembler/src/main.c b/assembler/src/main.c
index edba5c3..f534112 100644
--- a/assembler/src/main.c
+++ b/assembler/src/main.c
@@ -351,12 +351,12 @@ int main(int argc, char **argv)
 				entry1->inst_offset - entry->inst_offset;
 			    int delta = (entry->instruction.header.opcode == BRW_OPCODE_JMPI ? 1 : 0);
                             if (gen_level >= 5)
-                                    entry->instruction.bits3.branch.JIP = 2 * (offset - delta); // bspec: the jump distance in number of eight-byte units
+                                    entry->instruction.bits3.JIP = 2 * (offset - delta); // bspec: the jump distance in number of eight-byte units
                             else
-                                    entry->instruction.bits3.branch.JIP = offset - delta;
+                                    entry->instruction.bits3.JIP = offset - delta;
 
                             if (entry->instruction.header.opcode == BRW_OPCODE_ELSE)
-                                    entry->instruction.bits3.branch.UIP = 1;
+                                    entry->instruction.bits3.branch_2_offset.UIP = 1;
 			    found = 1;
 			    break;
 			}