From: Derek Schuff <dschuff@google.com>
Date: Mon, 4 Apr 2016 18:03:29 +0000 (+0000)
Subject: Replace MachineRegisterInfo::isSSA() with a MachineFunctionProperty
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=73900c6876ab794348e828312622bbdf536df8b4;p=platform%2Fupstream%2Fllvm.git

Replace MachineRegisterInfo::isSSA() with a MachineFunctionProperty

Use the MachineFunctionProperty mechanism to indicate whether a MachineFunction
is in SSA form instead of a custom method on MachineRegisterInfo. NFC

Differential Revision: http://reviews.llvm.org/D18574

llvm-svn: 265318
---

diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 27d2e0a..3fe3cd5 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -105,8 +105,8 @@ public:
   // that the property hold, but not that it does not hold.
 
   // Property descriptions:
-  // IsSSA (currently unused, intended to eventually replace
-  // MachineRegisterInfo::isSSA())
+  // IsSSA: True when the machine function is in SSA form and virtual registers
+  // have a single def.
   // TracksLiveness: (currently unsued, intended to eventually replace
   // MachineRegisterInfo::tracksLiveness())
   // AllVRegsAllocated: All virtual registers have been allocated; i.e. all
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index 704fb02..554406b 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -40,13 +40,9 @@ public:
   };
 
 private:
-  const MachineFunction *MF;
+  MachineFunction *MF;
   Delegate *TheDelegate;
 
-  /// IsSSA - True when the machine function is in SSA form and virtual
-  /// registers have a single def.
-  bool IsSSA;
-
   /// TracksLiveness - True while register liveness is being tracked accurately.
   /// Basic block live-in lists, kill flags, and implicit defs may not be
   /// accurate when after this flag is cleared.
@@ -126,7 +122,7 @@ private:
   MachineRegisterInfo(const MachineRegisterInfo&) = delete;
   void operator=(const MachineRegisterInfo&) = delete;
 public:
-  explicit MachineRegisterInfo(const MachineFunction *MF);
+  explicit MachineRegisterInfo(MachineFunction *MF);
 
   const TargetRegisterInfo *getTargetRegisterInfo() const {
     return MF->getSubtarget().getRegisterInfo();
@@ -160,10 +156,15 @@ public:
   // The TwoAddressInstructionPass and PHIElimination passes take the machine
   // function out of SSA form when they introduce multiple defs per virtual
   // register.
-  bool isSSA() const { return IsSSA; }
+  bool isSSA() const {
+    return MF->getProperties().hasProperty(
+        MachineFunctionProperties::Property::IsSSA);
+  }
 
   // leaveSSA - Indicates that the machine function is no longer in SSA form.
-  void leaveSSA() { IsSSA = false; }
+  void leaveSSA() {
+    MF->getProperties().clear(MachineFunctionProperties::Property::IsSSA);
+  }
 
   /// tracksLiveness - Returns true when tracking register liveness accurately.
   ///
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index a8475d2..52f9a1d 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -57,20 +57,17 @@ void MachineFunctionInitializer::anchor() {}
 void MachineFunctionProperties::print(raw_ostream &ROS) const {
   // Leave this function even in NDEBUG as an out-of-line anchor.
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-  if (!Properties.any()) {
-    ROS << "(empty)";
-    return;
-  }
   for (BitVector::size_type i = 0; i < Properties.size(); ++i) {
-    if (Properties[i]) {
-      switch(static_cast<Property>(i)) {
-        case Property::AllVRegsAllocated:
-          ROS << "AllVRegsAllocated ";
-          break;
-        default:
-          // TODO: Implement IsSSA/TracksLiveness when we make them properties.
-          llvm_unreachable("Unexpected value for property enum");
-      }
+    bool HasProperty = Properties[i];
+    switch(static_cast<Property>(i)) {
+      case Property::IsSSA:
+        ROS << (HasProperty ? "SSA, " : "Post SSA, ");
+        break;
+      case Property::AllVRegsAllocated:
+        ROS << (HasProperty ? "AllVRegsAllocated" : "HasVRegs");
+        break;
+      default:
+        break;
     }
   }
 #endif
@@ -91,6 +88,8 @@ MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM,
                                  unsigned FunctionNum, MachineModuleInfo &mmi)
     : Fn(F), Target(TM), STI(TM.getSubtargetImpl(*F)), Ctx(mmi.getContext()),
       MMI(mmi) {
+  // Assume the function starts in SSA form.
+  Properties.set(MachineFunctionProperties::Property::IsSSA);
   if (STI->getRegisterInfo())
     RegInfo = new (Allocator) MachineRegisterInfo(this);
   else
@@ -396,9 +395,8 @@ void MachineFunction::print(raw_ostream &OS, SlotIndexes *Indexes) const {
   getProperties().print(OS);
   OS << "> : ";
   if (RegInfo) {
-    OS << (RegInfo->isSSA() ? "SSA" : "Post SSA");
     if (!RegInfo->tracksLiveness())
-      OS << ", not tracking liveness";
+      OS << "not tracking liveness";
   }
   OS << '\n';
 
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index 8521bee..536577c 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -24,8 +24,8 @@ using namespace llvm;
 // Pin the vtable to this file.
 void MachineRegisterInfo::Delegate::anchor() {}
 
-MachineRegisterInfo::MachineRegisterInfo(const MachineFunction *MF)
-  : MF(MF), TheDelegate(nullptr), IsSSA(true), TracksLiveness(true),
+MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
+  : MF(MF), TheDelegate(nullptr), TracksLiveness(true),
     TracksSubRegLiveness(false) {
   unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
   VRegInfo.reserve(256);