From: Jie Zhang <jie.zhang@analog.com>
Date: Fri, 18 Nov 2005 14:21:29 +0000 (+0000)
Subject: 	* config/bfin-defs.h (IS_BREG, IS_LREG): New macros.
X-Git-Tag: gdb-csl-20060226-branchpoint~711
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=73562ad0c76e78ffc052085507181352daea9e7c;p=platform%2Fupstream%2Fbinutils.git

	* config/bfin-defs.h (IS_BREG, IS_LREG): New macros.
	* config/bfin-parse.y (asm_1): Check register type for load immediate
	instruction.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index e452f79..f994538 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2005-11-18  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-defs.h (IS_BREG, IS_LREG): New macros.
+	* config/bfin-parse.y (asm_1): Check register type for load immediate
+	instruction.
+
 2005-11-17  Alexandre Oliva  <aoliva@redhat.com>
 
 	* config/tc-ppc.c (ppc_frob_file_before_adjust): Do not reference
diff --git a/gas/config/bfin-defs.h b/gas/config/bfin-defs.h
index 221e8c4..46ae61e 100644
--- a/gas/config/bfin-defs.h
+++ b/gas/config/bfin-defs.h
@@ -199,6 +199,8 @@ enum reg_class
 #define IS_PREG(r)       _TYPECHECK(r, P)
 #define IS_IREG(r)       (((r).regno & 0xf4) == T_REG_I)
 #define IS_MREG(r)       (((r).regno & 0xf4) == T_REG_M)
+#define IS_BREG(r)       (((r).regno & 0xf4) == T_REG_B)
+#define IS_LREG(r)       (((r).regno & 0xf4) == T_REG_L)
 #define IS_CREG(r)       ((r).regno == REG_LC0 || (r).regno == REG_LC1)
 #define IS_ALLREG(r)     ((r).regno < T_NOGROUP)
 
diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index 7751b68..f5f1022 100644
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -1189,8 +1189,14 @@ asm_1:
 	| HALF_REG ASSIGN expr
 	{
 	  notethat ("LDIMMhalf: pregs_half = imm16\n");
+
+	  if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
+	      && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
+	    return yyerror ("Wrong register for load immediate");
+
 	  if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
 	    return yyerror ("Constant out of range");
+
 	  $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
 	}
 
@@ -1206,6 +1212,10 @@ asm_1:
 
 	| REG ASSIGN expr xpmod1
 	{
+	  if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
+	      && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
+	    return yyerror ("Wrong register for load immediate");
+
 	  if ($4.r0 == 0)
 	    {
 	      /* 7 bit immediate value if possible.