From: Thomas Petazzoni Date: Mon, 23 Dec 2013 08:48:10 +0000 (+0100) Subject: ARM: mvebu: fix register length for Armada XP PMSU X-Git-Tag: v3.14-rc1~36^2~12^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=72c3e2295c1955b9d188dbaf910bc67a4dc2e3e5;p=kernel%2Fkernel-generic.git ARM: mvebu: fix register length for Armada XP PMSU The per-CPU PMSU registers documented in the datasheet start at 0x22100 and the last register for CPU3 is at 0x22428. However, the DT informations use <0x22100 0x430>, which makes the region end at 0x22530 and not 0x22430. Moreover, looking at the datasheet, we can see that the registers for CPU0 start at 0x22100, for CPU1 at 0x22200, for CPU2 at 0x22300 and for CPU3 at 0x22400. It seems clear that 0x100 bytes of registers have been used per CPU. Therefore, this commit reduces the length of the PMSU per-CPU register area from the incorrect 0x430 bytes to a more logical 0x400 bytes. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 4919fb8..b8b84a2 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -113,7 +113,7 @@ armada-370-xp-pmsu@22000 { compatible = "marvell,armada-370-xp-pmsu"; - reg = <0x22100 0x430>, <0x20800 0x20>; + reg = <0x22100 0x400>, <0x20800 0x20>; }; eth2: ethernet@30000 {