From: Zhenyu Wang <zhenyuw@linux.intel.com>
Date: Thu, 30 Sep 2010 02:49:47 +0000 (+0800)
Subject: i965: always set tiling for fbo depth buffer on sandybridge
X-Git-Tag: mesa-7.10~1151^2~486
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=72b368ae69bc037681ab4e458296c07cb04349be;p=platform%2Fupstream%2Fmesa.git

i965: always set tiling for fbo depth buffer on sandybridge

Sandybridge requires depth buffer must be tiling.

Fix 'fbo_firecube' demo.
---

diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 9845850..8c0491d 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -102,7 +102,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
 {
    struct intel_context *intel = intel_context(ctx);
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-   int cpp;
+   int cpp, tiling;
 
    ASSERT(rb->Name != 0);
 
@@ -176,7 +176,13 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
    /* alloc hardware renderbuffer */
    DBG("Allocating %d x %d Intel RBO\n", width, height);
 
-   irb->region = intel_region_alloc(intel->intelScreen, I915_TILING_NONE, cpp,
+   tiling = I915_TILING_NONE;
+
+   /* Gen6 requires depth must be tiling */
+   if (intel->gen >= 6 && rb->Format == MESA_FORMAT_S8_Z24)
+       tiling = I915_TILING_Y;
+
+   irb->region = intel_region_alloc(intel->intelScreen, tiling, cpp,
 				    width, height, GL_TRUE);
    if (!irb->region)
       return GL_FALSE;       /* out of memory? */