From: Topi Pohjolainen <topi.pohjolainen@intel.com>
Date: Wed, 6 Jul 2016 09:29:41 +0000 (+0300)
Subject: i965: Refactor lossless compression state tracking
X-Git-Tag: upstream/17.1.0~4345
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=71d48d6f42c3ae03b797c25d58f2f1f4dcd8fc29;p=platform%2Fupstream%2Fmesa.git

i965: Refactor lossless compression state tracking

Essentially this moves fast clear state update away from surface
state setup into brw_postdraw_set_buffers_need_resolve() that gets
called just after draw submission.
Calling intel_miptree_used_for_rendering() can be drop for gen6
and earlier as it is no-op.

v2: Rebased on top current master setting the state in
    blorp_surf_for_miptree().

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
---

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 56a30b4..556f2c0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -220,12 +220,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
       }
    }
 
-   if (is_render_target) {
-      intel_miptree_used_for_rendering(mt);
-
-      if (surf->aux_usage == ISL_AUX_USAGE_CCS_E)
-         mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
-   }
+   if (is_render_target)
+      intel_miptree_used_for_rendering(brw, mt);
 
    if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
       /* We only really need a clear color if we also have an auxiliary
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 7904ef5..08a9fbc 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -388,10 +388,7 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
 
       if (irb) {
          brw_render_cache_set_add_bo(brw, irb->mt->bo);
-
-         if (intel_miptree_is_lossless_compressed(brw, irb->mt)) {
-            irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
-         }
+         intel_miptree_used_for_rendering(brw, irb->mt);
       }
    }
 }
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index d40ccbf..ec434c7 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -205,7 +205,6 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
    }
 
    assert(brw_render_target_supported(brw, rb));
-   intel_miptree_used_for_rendering(mt);
 
    mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
@@ -992,8 +991,6 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
       }
    }
 
-   intel_miptree_used_for_rendering(irb->mt);
-
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset);
 
    format = brw->render_target_format[rb_format];
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 943c5a5..7ad074c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -967,13 +967,15 @@ intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
  * for rendering.
  */
 static inline void
-intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
+intel_miptree_used_for_rendering(const struct brw_context *brw,
+                                 struct intel_mipmap_tree *mt)
 {
    /* If the buffer was previously in fast clear state, change it to
     * unresolved state, since it won't be guaranteed to be clear after
     * rendering occurs.
     */
-   if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
+   if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR ||
+      intel_miptree_is_lossless_compressed(brw, mt))
       mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 }