From: Andreas Oetken Date: Mon, 20 Apr 2015 22:16:38 +0000 (+0200) Subject: altera tse: Error-Bit on tx-avalon-stream always set. X-Git-Tag: v4.1-rc1~55^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=71cd26e76a9514715df7880db0a8f7c37c17149a;p=platform%2Fkernel%2Flinux-exynos.git altera tse: Error-Bit on tx-avalon-stream always set. The Error-Bit on the avalon streaming interface of the tx-dma-channel was always set. In SGMII configurations this leads to error-symbols on the PCS and packet-rejection on the receiver side (e.g. SGMII/1000Base-X connected switch). This only applies to the tse-configuration with MSGDMA. This issue was detected and fixed on a custom board with a direct connection to a Marvell switch in SGMII-PHY-Mode. (incl. custom patches for SGMII-PCS). According to the datasheet if ff_tx_err (avalon-streaming) is set it is forwarded to gm_tx_err. As a result the PCS is forwarding the error by sending a "/V/"-caracter. Signed-off-by: Andreas Oetken Signed-off-by: David S. Miller --- diff --git a/drivers/net/ethernet/altera/altera_msgdmahw.h b/drivers/net/ethernet/altera/altera_msgdmahw.h index e335626..eba070f 100644 --- a/drivers/net/ethernet/altera/altera_msgdmahw.h +++ b/drivers/net/ethernet/altera/altera_msgdmahw.h @@ -72,7 +72,6 @@ struct msgdma_extended_desc { #define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \ MSGDMA_DESC_CTL_GEN_EOP | \ MSGDMA_DESC_CTL_TR_COMP_IRQ | \ - MSGDMA_DESC_CTL_TR_ERR_IRQ | \ MSGDMA_DESC_CTL_GO) #define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \