From: James Greenhalgh Date: Tue, 18 Feb 2020 14:45:49 +0000 (+0000) Subject: aarch64: Move vmull_* to intrinsics X-Git-Tag: upstream/12.2.0~18317 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=71c82d0e18de01a3b439a77f0e28ae8c0d5247b5;p=platform%2Fupstream%2Fgcc.git aarch64: Move vmull_* to intrinsics Move some arm_neon.h functions which currently use assembly over to intrinsics. 2020-02-18 James Greenhalgh gcc/ * config/aarch64/aarch64-simd-builtins.def (intrinsic_vec_smult_lo_): New. (intrinsic_vec_umult_lo_): Likewise. (vec_widen_smult_hi_): Likewise. (vec_widen_umult_hi_): Likewise. * config/aarch64/aarch64-simd.md (aarch64_intrinsic_vec_mult_lo_): New. * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics. (vmull_high_s16): Likewise. (vmull_high_s32): Likewise. (vmull_high_u8): Likewise. (vmull_high_u16): Likewise. (vmull_high_u32): Likewise. (vmull_s8): Likewise. (vmull_s16): Likewise. (vmull_s32): Likewise. (vmull_u8): Likewise. (vmull_u16): Likewise. (vmull_u32): Likewise. gcc/testsuite/ * gcc.target/aarch64/vmull_high.c: New. --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 731bae4..c2778e1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,25 @@ +2020-02-18 James Greenhalgh + + * config/aarch64/aarch64-simd-builtins.def + (intrinsic_vec_smult_lo_): New. + (intrinsic_vec_umult_lo_): Likewise. + (vec_widen_smult_hi_): Likewise. + (vec_widen_umult_hi_): Likewise. + * config/aarch64/aarch64-simd.md + (aarch64_intrinsic_vec_mult_lo_): New. + * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics. + (vmull_high_s16): Likewise. + (vmull_high_s32): Likewise. + (vmull_high_u8): Likewise. + (vmull_high_u16): Likewise. + (vmull_high_u32): Likewise. + (vmull_s8): Likewise. + (vmull_s16): Likewise. + (vmull_s32): Likewise. + (vmull_u8): Likewise. + (vmull_u16): Likewise. + (vmull_u32): Likewise. + 2020-02-18 Martin Liska * value-prof.c (stream_out_histogram_value): Restore LTO PGO diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index fe3c7f1..d8bb96f 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -185,6 +185,12 @@ BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0) BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0) + BUILTIN_VD_BHSI (BINOP, intrinsic_vec_smult_lo_, 0) + BUILTIN_VD_BHSI (BINOPU, intrinsic_vec_umult_lo_, 0) + + BUILTIN_VQW (BINOP, vec_widen_smult_hi_, 10) + BUILTIN_VQW (BINOPU, vec_widen_umult_hi_, 10) + BUILTIN_VSD_HSI (BINOP, sqdmull, 0) BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0) BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 33d705a..89aaf8c 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1839,6 +1839,17 @@ [(set_attr "type" "neon_mul__long")] ) +(define_insn "aarch64_intrinsic_vec_mult_lo_" + [(set (match_operand: 0 "register_operand" "=w") + (mult: (ANY_EXTEND: + (match_operand:VD_BHSI 1 "register_operand" "w")) + (ANY_EXTEND: + (match_operand:VD_BHSI 2 "register_operand" "w"))))] + "TARGET_SIMD" + "mull\\t%0., %1., %2." + [(set_attr "type" "neon_mul__long")] +) + (define_expand "vec_widen_mult_lo_" [(match_operand: 0 "register_operand") (ANY_EXTEND: (match_operand:VQW 1 "register_operand")) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index a6bcdf1..6a2220a 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -9221,72 +9221,42 @@ __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_high_s8 (int8x16_t __a, int8x16_t __b) { - int16x8_t __result; - __asm__ ("smull2 %0.8h,%1.16b,%2.16b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_vec_widen_smult_hi_v16qi (__a, __b); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_high_s16 (int16x8_t __a, int16x8_t __b) { - int32x4_t __result; - __asm__ ("smull2 %0.4s,%1.8h,%2.8h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_vec_widen_smult_hi_v8hi (__a, __b); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_high_s32 (int32x4_t __a, int32x4_t __b) { - int64x2_t __result; - __asm__ ("smull2 %0.2d,%1.4s,%2.4s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_vec_widen_smult_hi_v4si (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_high_u8 (uint8x16_t __a, uint8x16_t __b) { - uint16x8_t __result; - __asm__ ("umull2 %0.8h,%1.16b,%2.16b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_vec_widen_umult_hi_v16qi_uuu (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_high_u16 (uint16x8_t __a, uint16x8_t __b) { - uint32x4_t __result; - __asm__ ("umull2 %0.4s,%1.8h,%2.8h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_vec_widen_umult_hi_v8hi_uuu (__a, __b); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_high_u32 (uint32x4_t __a, uint32x4_t __b) { - uint64x2_t __result; - __asm__ ("umull2 %0.2d,%1.4s,%2.4s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_vec_widen_umult_hi_v4si_uuu (__a, __b); } #define vmull_lane_s16(a, b, c) \ @@ -9457,72 +9427,42 @@ __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_s8 (int8x8_t __a, int8x8_t __b) { - int16x8_t __result; - __asm__ ("smull %0.8h, %1.8b, %2.8b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_intrinsic_vec_smult_lo_v8qi (__a, __b); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_s16 (int16x4_t __a, int16x4_t __b) { - int32x4_t __result; - __asm__ ("smull %0.4s, %1.4h, %2.4h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_intrinsic_vec_smult_lo_v4hi (__a, __b); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_s32 (int32x2_t __a, int32x2_t __b) { - int64x2_t __result; - __asm__ ("smull %0.2d, %1.2s, %2.2s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_intrinsic_vec_smult_lo_v2si (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_u8 (uint8x8_t __a, uint8x8_t __b) { - uint16x8_t __result; - __asm__ ("umull %0.8h, %1.8b, %2.8b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_intrinsic_vec_umult_lo_v8qi_uuu (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_u16 (uint16x4_t __a, uint16x4_t __b) { - uint32x4_t __result; - __asm__ ("umull %0.4s, %1.4h, %2.4h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_intrinsic_vec_umult_lo_v4hi_uuu (__a, __b); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_u32 (uint32x2_t __a, uint32x2_t __b) { - uint64x2_t __result; - __asm__ ("umull %0.2d, %1.2s, %2.2s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_intrinsic_vec_umult_lo_v2si_uuu (__a, __b); } __extension__ extern __inline int16x4_t diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 600ac38..de7c6c0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-02-18 James Greenhalgh + + * gcc.target/aarch64/vmull_high.c: New. + 2020-02-18 Marek Polacek PR c++/93817 diff --git a/gcc/testsuite/gcc.target/aarch64/vmull_high.c b/gcc/testsuite/gcc.target/aarch64/vmull_high.c new file mode 100644 index 0000000..cddb7e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vmull_high.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O3" } */ + +#include + +int64x2_t +doit (int8x16_t a) +{ + int16x8_t b = vmull_high_s8 (a, a); + int32x4_t c = vmull_high_s16 (b, b); + return vmull_high_s32 (c, c); +} + +uint64x2_t +douit (uint8x16_t a) +{ + uint16x8_t b = vmull_high_u8 (a, a); + uint32x4_t c = vmull_high_u16 (b, b); + return vmull_high_u32 (c, c); +} + +/* { dg-final { scan-assembler-times "smull2\[ |\t\]*v" 3} } */ +/* { dg-final { scan-assembler-times "umull2\[ |\t\]*v" 3} } */