From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Wed, 17 May 2023 07:52:35 +0000 (+0200)
Subject: amd/drm-shim: add navi21
X-Git-Tag: upstream/23.3.3~8397
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=714ae976692c1e7c635a1def425d3623998f94dc;p=platform%2Fupstream%2Fmesa.git

amd/drm-shim: add navi21

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23072>
---

diff --git a/src/amd/drm-shim/amdgpu_devices.c b/src/amd/drm-shim/amdgpu_devices.c
index ce10689..5bd36bb 100644
--- a/src/amd/drm-shim/amdgpu_devices.c
+++ b/src/amd/drm-shim/amdgpu_devices.c
@@ -1317,6 +1317,135 @@ const struct amdgpu_device amdgpu_devices[] = {
             .max_allocation = 24930671616,
          },
       },
+   },
+   {
+      .name = "navi21",
+      .radeon_family = CHIP_NAVI21,
+      .hw_ip_gfx = {
+         .hw_ip_version_major = 10,
+         .hw_ip_version_minor = 0,
+         .capabilities_flags = 0llu,
+         .ib_start_alignment = 32,
+         .ib_size_alignment = 32,
+         .available_rings = 0x1,
+         .ip_discovery_version = 0xa0300,
+      },
+      .hw_ip_compute = {
+         .hw_ip_version_major = 10,
+         .hw_ip_version_minor = 0,
+         .capabilities_flags = 0llu,
+         .ib_start_alignment = 32,
+         .ib_size_alignment = 32,
+         .available_rings = 0xf,
+         .ip_discovery_version = 0xa0300,
+      },
+      .fw_gfx_me = {
+         .ver = 64,
+         .feature = 42,
+      },
+      .fw_gfx_pfp = {
+         .ver = 95,
+         .feature = 42,
+      },
+      .fw_gfx_mec = {
+         .ver = 104,
+         .feature = 42,
+      },
+      .mmr_regs = {
+         0x263e, 0xffffffff, 0x00000444,
+      },
+      .mmr_reg_count = 1,
+      .dev = {
+         .device_id = 0x73bf,
+         .chip_rev = 0x01,
+         .external_rev = 0x29,
+         .pci_rev = 0xc3,
+         .family = AMDGPU_FAMILY_NV,
+         .num_shader_engines = 4,
+         .num_shader_arrays_per_engine = 2,
+         .gpu_counter_freq = 100000,
+         .max_engine_clock = 2475000llu,
+         .max_memory_clock = 1000000llu,
+         .cu_active_number = 60,
+         .cu_ao_mask = 0x3ffff,
+         .cu_bitmap = {
+            { 0x3ff, 0x3ff, 0x0, 0x0, },
+            { 0x0, 0x0, 0x0, 0x0, },
+            { 0x3ff, 0x3ff, 0x0, 0x0, },
+            { 0x3ff, 0x3ff, 0x0, 0x0, },
+         },
+         .enabled_rb_pipes_mask = 0xff0f,
+         .num_rb_pipes = 16,
+         .num_hw_gfx_contexts = 8,
+         .pcie_gen = 3,
+         .ids_flags = 0x0llu,
+         .virtual_address_offset = 0x200000llu,
+         .virtual_address_max = 0x800000000000llu,
+         .virtual_address_alignment = 4096,
+         .pte_fragment_size = 2097152,
+         .gart_page_size = 4096,
+         .ce_ram_size = 65536,
+         .vram_type = 9,
+         .vram_bit_width = 256,
+         .vce_harvest_config = 0,
+         .gc_double_offchip_lds_buf = 1,
+         .prim_buf_gpu_addr = 0llu,
+         .pos_buf_gpu_addr = 0llu,
+         .cntl_sb_buf_gpu_addr = 0llu,
+         .param_buf_gpu_addr = 0llu,
+         .prim_buf_size = 0,
+         .pos_buf_size = 0,
+         .cntl_sb_buf_size = 0,
+         .param_buf_size = 0,
+         .wave_front_size = 32,
+         .num_shader_visible_vgprs = 1024,
+         .num_cu_per_sh = 10,
+         .num_tcc_blocks = 16,
+         .gs_vgt_table_depth = 32,
+         .gs_prim_buffer_depth = 1792,
+         .max_gs_waves_per_vgt = 32,
+         .pcie_num_lanes = 16,
+         .cu_ao_bitmap = {
+            { 0x3ff, 0x3ff, 0x0, 0x0, },
+            { 0x0, 0x0, 0x0, 0x0, },
+            { 0x3ff, 0x3ff, 0x0, 0x0, },
+            { 0x3ff, 0x3ff, 0x0, 0x0, },
+         },
+         .high_va_offset = 0xffff800000000000llu,
+         .high_va_max = 0xffffffffffe00000llu,
+         .pa_sc_tile_steering_override = 0,
+         .tcc_disabled_mask = 0llu,
+         .min_engine_clock = 500000llu,
+         .min_memory_clock = 96000llu,
+         .tcp_cache_size = 0,
+         .num_sqc_per_wgp = 0,
+         .sqc_data_cache_size = 0,
+         .sqc_inst_cache_size = 0,
+         .gl1c_cache_size = 0,
+         .gl2c_cache_size = 0,
+         .mall_size = 134217728llu,
+         .enabled_rb_pipes_mask_hi = 0,
+      },
+      .mem = {
+         .vram = {
+            .total_heap_size = 17163091968,
+            .usable_heap_size = 17128448000,
+            .heap_usage = 817770496,
+            .max_allocation = 12846336000,
+         },
+         .cpu_accessible_vram = {
+            .total_heap_size = 268435456,
+            .usable_heap_size = 273055744,
+            .heap_usage = 246521856,
+            .max_allocation = 204791808,
+         },
+         .gtt = {
+            .total_heap_size = 16746784768,
+            .usable_heap_size = 16733624320,
+            .heap_usage = 499445760,
+            .max_allocation = 12550218240,
+         },
+      },
    }
 };