From: Francisco Jerez <currojerez@riseup.net>
Date: Mon, 9 Jan 2017 22:14:02 +0000 (-0800)
Subject: intel/fs: Fix fs_builder::sample_mask_reg() for 32-wide FS dispatch.
X-Git-Tag: upstream/19.0.0~4183
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7144247c2c349e7013ec33cfb46eb3e84b63007a;p=platform%2Fupstream%2Fmesa.git

intel/fs: Fix fs_builder::sample_mask_reg() for 32-wide FS dispatch.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
---

diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h
index 4203c8c..7bee2aa 100644
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -235,14 +235,14 @@ namespace brw {
       src_reg
       sample_mask_reg() const
       {
-         assert(shader->stage != MESA_SHADER_FRAGMENT ||
-                group() + dispatch_width() <= 16);
          if (shader->stage != MESA_SHADER_FRAGMENT) {
             return brw_imm_d(0xffffffff);
          } else if (brw_wm_prog_data(shader->stage_prog_data)->uses_kill) {
             return brw_flag_reg(0, 1);
          } else {
-            return retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD);
+            assert(shader->devinfo->gen >= 6 && dispatch_width() <= 16);
+            return retype(brw_vec1_grf((_group >= 16 ? 2 : 1), 7),
+                          BRW_REGISTER_TYPE_UD);
          }
       }