From: Jakub Jelinek Date: Sat, 26 May 2018 22:04:50 +0000 (+0200) Subject: re PR target/85918 (Conversions to/from [unsigned] long long are not vectorized for... X-Git-Tag: upstream/12.2.0~31470 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=70d22cdd77fdd3a11514735a7992b5f07bd50159;p=platform%2Fupstream%2Fgcc.git re PR target/85918 (Conversions to/from [unsigned] long long are not vectorized for AVX512DQ target) PR target/85918 * config/i386/i386.md (fixunssuffix, floatunssuffix): New code attributes. * config/i386/sse.md (float2): Rename to ... (float2): ... this. (float2): Rename to ... (float2): ... this. (*floatv2div2sf2): Rename to ... (*floatv2div2sf2): ... this. (floatv2div2sf2_mask): Rename to ... (floatv2div2sf2_mask): ... this. (*floatv2div2sf2_mask_1): Rename to ... (*floatv2div2sf2_mask_1): ... this. (fix_truncv8dfv8si2): Rename to ... (fix_truncv8dfv8si2): ... this. (fix_trunc2): Rename to ... (fix_trunc2): ... this. (fix_trunc2): Rename to ... (fix_trunc2): ... this. (fix_truncv2sfv2di2): Rename to ... (fix_truncv2sfv2di2): ... this. (vec_pack_ufix_trunc_): Use gen_fixuns_truncv8dfv8si2 instead of gen_ufix_truncv8dfv8si2. * config/i386/i386-builtin.def (__builtin_ia32_cvttpd2uqq256_mask, __builtin_ia32_cvttpd2uqq128_mask, __builtin_ia32_cvttps2uqq256_mask, __builtin_ia32_cvttps2uqq128_mask, __builtin_ia32_cvtuqq2ps256_mask, __builtin_ia32_cvtuqq2ps128_mask, __builtin_ia32_cvtuqq2pd256_mask, __builtin_ia32_cvtuqq2pd128_mask, __builtin_ia32_cvttpd2udq512_mask, __builtin_ia32_cvtuqq2ps512_mask, __builtin_ia32_cvtuqq2pd512_mask, __builtin_ia32_cvttps2uqq512_mask, __builtin_ia32_cvttpd2uqq512_mask): Use fixuns instead ufix or floatuns instead ufloat in CODE_FOR_ names. * gcc.target/i386/avx512dq-pr85918.c: New test. From-SVN: r260797 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fdfd41a..3d16ca7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,48 @@ +2018-05-27 Jakub Jelinek + + PR target/85918 + * config/i386/i386.md (fixunssuffix, floatunssuffix): New code + attributes. + * config/i386/sse.md + (float2): + Rename to ... + (float2): + ... this. + (float2): + Rename to ... + (float2): + ... this. + (*floatv2div2sf2): Rename to ... + (*floatv2div2sf2): ... this. + (floatv2div2sf2_mask): Rename to ... + (floatv2div2sf2_mask): ... this. + (*floatv2div2sf2_mask_1): Rename to ... + (*floatv2div2sf2_mask_1): ... this. + (fix_truncv8dfv8si2): Rename + to ... + (fix_truncv8dfv8si2): + ... this. + (fix_trunc2): + Rename to ... + (fix_trunc2): + ... this. + (fix_trunc2): + Rename to ... + (fix_trunc2): + ... this. + (fix_truncv2sfv2di2): Rename to ... + (fix_truncv2sfv2di2): ... this. + (vec_pack_ufix_trunc_): Use gen_fixuns_truncv8dfv8si2 instead of + gen_ufix_truncv8dfv8si2. + * config/i386/i386-builtin.def (__builtin_ia32_cvttpd2uqq256_mask, + __builtin_ia32_cvttpd2uqq128_mask, __builtin_ia32_cvttps2uqq256_mask, + __builtin_ia32_cvttps2uqq128_mask, __builtin_ia32_cvtuqq2ps256_mask, + __builtin_ia32_cvtuqq2ps128_mask, __builtin_ia32_cvtuqq2pd256_mask, + __builtin_ia32_cvtuqq2pd128_mask, __builtin_ia32_cvttpd2udq512_mask, + __builtin_ia32_cvtuqq2ps512_mask, __builtin_ia32_cvtuqq2pd512_mask, + __builtin_ia32_cvttps2uqq512_mask, __builtin_ia32_cvttpd2uqq512_mask): + Use fixuns instead ufix or floatuns instead ufloat in CODE_FOR_ names. + 2018-05-24 H.J. Lu PR target/85900 diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 1b9c63a..1404129 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -1612,8 +1612,8 @@ BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_db BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI) -BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI) -BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI) +BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fixuns_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI) +BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fixuns_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI) @@ -1622,8 +1622,8 @@ BDESC (OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin BDESC (OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI) -BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI) -BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI) +BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fixuns_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI) +BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fixuns_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI) BDESC (OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI) BDESC (OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI) BDESC (OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI) @@ -1965,12 +1965,12 @@ BDESC (OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_ BDESC (OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_UQI) -BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_UQI) -BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_UQI) +BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatunsv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_UQI) +BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatunsv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_UQI) -BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_UQI) -BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_UQI) +BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatunsv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_UQI) +BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatunsv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_UQI) BDESC (OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI) BDESC (OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI) BDESC (OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI) @@ -2667,7 +2667,7 @@ BDESC (OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvt BDESC (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT) BDESC (OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT) BDESC (OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT) -BDESC (OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT) +BDESC (OPTION_MASK_ISA_AVX512F, CODE_FOR_fixuns_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT) BDESC (OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT) BDESC (OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT) BDESC (OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT) @@ -2797,13 +2797,13 @@ BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__b BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT) BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT) BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT) -BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT) +BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatunsv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT) BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT) -BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT) +BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatunsv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT) BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT) -BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT) +BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fixuns_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT) BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT) -BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT) +BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fixuns_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT) BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT) BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index bde3c34..12995be 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -981,10 +981,12 @@ ;; Used in signed and unsigned fix. (define_code_iterator any_fix [fix unsigned_fix]) (define_code_attr fixsuffix [(fix "") (unsigned_fix "u")]) +(define_code_attr fixunssuffix [(fix "") (unsigned_fix "uns")]) ;; Used in signed and unsigned float. (define_code_iterator any_float [float unsigned_float]) (define_code_attr floatsuffix [(float "") (unsigned_float "u")]) +(define_code_attr floatunssuffix [(float "") (unsigned_float "uns")]) ;; All integer modes. (define_mode_iterator SWI1248x [QI HI SI DI]) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a11180f..ed37b98 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4853,7 +4853,7 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) -(define_insn "float2" +(define_insn "float2" [(set (match_operand:VF2_AVX512VL 0 "register_operand" "=v") (any_float:VF2_AVX512VL (match_operand: 1 "nonimmediate_operand" "")))] @@ -4863,7 +4863,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -;; For float insn patterns +;; For float insn patterns (define_mode_attr qq2pssuff [(V8SF "") (V4SF "{y}")]) @@ -4877,7 +4877,7 @@ [(V8SF "XI") (V4SF "OI") (V8DF "OI") (V4DF "TI")]) -(define_insn "float2" +(define_insn "float2" [(set (match_operand:VF1_128_256VL 0 "register_operand" "=v") (any_float:VF1_128_256VL (match_operand: 1 "nonimmediate_operand" "")))] @@ -4887,7 +4887,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "*floatv2div2sf2" +(define_insn "*floatv2div2sf2" [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_concat:V4SF (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm")) @@ -4898,7 +4898,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "V4SF")]) -(define_insn "floatv2div2sf2_mask" +(define_insn "floatv2div2sf2_mask" [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_concat:V4SF (vec_merge:V2SF @@ -4914,7 +4914,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "V4SF")]) -(define_insn "*floatv2div2sf2_mask_1" +(define_insn "*floatv2div2sf2_mask_1" [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_concat:V4SF (vec_merge:V2SF @@ -5084,7 +5084,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "TI")]) -(define_insn "fix_truncv8dfv8si2" +(define_insn "fix_truncv8dfv8si2" [(set (match_operand:V8SI 0 "register_operand" "=v") (any_fix:V8SI (match_operand:V8DF 1 "" "")))] @@ -5123,7 +5123,7 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_insn "fix_trunc2" +(define_insn "fix_trunc2" [(set (match_operand: 0 "register_operand" "=v") (any_fix: (match_operand:VF2_AVX512VL 1 "" "")))] @@ -5155,7 +5155,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "fix_trunc2" +(define_insn "fix_trunc2" [(set (match_operand: 0 "register_operand" "=v") (any_fix: (match_operand:VF1_128_256VL 1 "" "")))] @@ -5165,7 +5165,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "fix_truncv2sfv2di2" +(define_insn "fix_truncv2sfv2di2" [(set (match_operand:V2DI 0 "register_operand" "=v") (any_fix:V2DI (vec_select:V2SF @@ -5961,8 +5961,8 @@ r1 = gen_reg_rtx (V8SImode); r2 = gen_reg_rtx (V8SImode); - emit_insn (gen_ufix_truncv8dfv8si2 (r1, operands[1])); - emit_insn (gen_ufix_truncv8dfv8si2 (r2, operands[2])); + emit_insn (gen_fixuns_truncv8dfv8si2 (r1, operands[1])); + emit_insn (gen_fixuns_truncv8dfv8si2 (r2, operands[2])); emit_insn (gen_avx_vec_concatv16si (operands[0], r1, r2)); } else diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4f38b53..a897b47 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-05-27 Jakub Jelinek + + PR target/85918 + * gcc.target/i386/avx512dq-pr85918.c: New test. + 2018-05-25 Jim Wilson * gcc.target/riscv/interrupt-1.c: New. diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-pr85918.c b/gcc/testsuite/gcc.target/i386/avx512dq-pr85918.c new file mode 100644 index 0000000..3c69f93 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-pr85918.c @@ -0,0 +1,42 @@ +/* PR target/85918 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx512dq -mavx512vl -fdump-tree-vect-details" } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ + +#define N 1024 + +long long ll[N]; +unsigned long long ull[N]; +double d[N]; + +void ll2d (void) +{ + int i; + + for (i = 0; i < N; i++) + d[i] = ll[i]; +} + +void ull2d (void) +{ + int i; + + for (i = 0; i < N; i++) + d[i] = ull[i]; +} + +void d2ll (void) +{ + int i; + + for (i = 0; i < N; i++) + ll[i] = d[i]; +} + +void d2ull (void) +{ + int i; + + for (i = 0; i < N; i++) + ull[i] = d[i]; +}