From: Alex Deucher Date: Fri, 20 May 2011 16:36:12 +0000 (-0400) Subject: drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices X-Git-Tag: 2.1b_release~3772^2~27 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6f15c506e0cec601fad9fabb7ded0d1811b8002f;p=platform%2Fkernel%2Fkernel-mfld-blackbay.git drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices If the ss clock is external, the CLK_REF bit needs to be set in the SetPixelClock parameters. This should fix DP failures in the channel equalization loop. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index dab06fb..f5819ba 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -815,6 +815,8 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc, args.v3.ucPostDiv = post_div; args.v3.ucPpll = pll_id; args.v3.ucMiscInfo = (pll_id << 2); + if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) + args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; args.v3.ucTransmitterId = encoder_id; args.v3.ucEncoderMode = encoder_mode; break;