From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 20 May 2018 16:31:17 +0000 (+0000)
Subject: clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
X-Git-Tag: v5.15~8657^2~4^3
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6ee3d385c263248ce0ab2fcd679835082530445d;p=platform%2Fkernel%2Flinux-starfive.git

clk: ingenic: jz4770: Add 150us delay after enabling VPU clock

This is required, as we must not use the AHB1 bus before it is stable.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---

diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index 314f314..bf46a0d 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -362,7 +362,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
 	[JZ4770_CLK_VPU] = {
 		"vpu", CGU_CLK_GATE,
 		.parents = { JZ4770_CLK_H1CLK, },
-		.gate = { CGU_REG_LCR, 30 },
+		.gate = { CGU_REG_LCR, 30, false, 150 },
 	},
 	[JZ4770_CLK_MMC0] = {
 		"mmc0", CGU_CLK_GATE,