From: Lucas Stach <dev@lynxeye.de>
Date: Mon, 6 May 2013 21:11:11 +0000 (-0600)
Subject: clk: tegra: add ac97 controller clock
X-Git-Tag: v3.10-rc3~13^2~13
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6ec3240047ee6a4b34f90d45e19ed179bc9b4a2e;p=profile%2Fivi%2Fkernel-x86-ivi.git

clk: tegra: add ac97 controller clock

AC97 controller clock is hardwired to pll_a_out0.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
---

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index d80c7cc..075db0c 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -872,6 +872,14 @@ static void __init tegra20_periph_clk_init(void)
 	struct clk *clk;
 	int i;
 
+	/* ac97 */
+	clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
+				    TEGRA_PERIPH_ON_APB,
+				    clk_base, 0, 3, &periph_l_regs,
+				    periph_clk_enb_refcnt);
+	clk_register_clkdev(clk, NULL, "tegra20-ac97");
+	clks[ac97] = clk;
+
 	/* apbdma */
 	clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
 				    0, 34, &periph_h_regs,