From: Nick Clifton <nickc@redhat.com>
Date: Fri, 13 Feb 1998 17:51:46 +0000 (+0000)
Subject: Regenerated after modifying cgen/m32r.cpu to remove WRITE_LR and WRITE_SRC
X-Git-Tag: gdb-4_18~3360
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6eacba2e77adff62f2f86381b9f0c09624464e29;p=external%2Fbinutils.git

Regenerated after modifying cgen/m32r.cpu to remove WRITE_LR and WRITE_SRC
attributes.
---

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index cd68ae6..8b89ca6 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+Fri Feb 13 09:50:32 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* m32r-opc.c: Regenerate. 
+	* m32r-opc.h: Regenerate. 
+
 Thu Feb 12 11:01:40 1998  Doug Evans  <devans@canuck.cygnus.com>
 
 	* cgen-opc.in (@arch@_cgen_lookup_insn): New argument alias_p.
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index f26f259..41651af 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -167,20 +167,6 @@ static const CGEN_ATTR_ENTRY MACH_attr[] =
   { 0, 0 }
 };
 
-static const CGEN_ATTR_ENTRY WRITE_LR_attr[] =
-{
-  { "NO", WRITE_LR_NO },
-  { "YES", WRITE_LR_YES },
-  { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY WRITE_SRC_attr[] =
-{
-  { "NO", WRITE_SRC_NO },
-  { "YES", WRITE_SRC_YES },
-  { 0, 0 }
-};
-
 /* start-sanitize-m32rx */
 static const CGEN_ATTR_ENTRY PIPE_attr[] =
 {
@@ -212,8 +198,6 @@ const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 /* start-sanitize-m32rx */
   { "PIPE", & PIPE_attr[0] },
 /* end-sanitize-m32rx */
-  { "WRITE_LR", & WRITE_LR_attr[0] },
-  { "WRITE_SRC", & WRITE_SRC_attr[0] },
   { "ALIAS", NULL },
   { "COND-CTI", NULL },
   { "FILL-SLOT", NULL },
@@ -1211,231 +1195,231 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "add", "add", SYN (0), FMT (0), 0xa0,
     & fmt_0_add_ops[0],
-    { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* add3 $dr,$sr,#$slo16 */
   {
     { 1, 1, 1, 1 },
     "add3", "add3", SYN (1), FMT (1), 0x80a00000,
     & fmt_1_add3_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* add3 $dr,$sr,$slo16 */
   {
     { 1, 1, 1, 1 },
     "add3.a", "add3", SYN (2), FMT (1), 0x80a00000,
     & fmt_1_add3_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* and $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "and", "and", SYN (0), FMT (0), 0xc0,
     & fmt_0_add_ops[0],
-    { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* and3 $dr,$sr,#$uimm16 */
   {
     { 1, 1, 1, 1 },
     "and3", "and3", SYN (3), FMT (2), 0x80c00000,
     & fmt_2_and3_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* and3 $dr,$sr,$uimm16 */
   {
     { 1, 1, 1, 1 },
     "and3.a", "and3", SYN (4), FMT (2), 0x80c00000,
     & fmt_2_and3_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* or $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "or", "or", SYN (0), FMT (0), 0xe0,
     & fmt_0_add_ops[0],
-    { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* or3 $dr,$sr,#$ulo16 */
   {
     { 1, 1, 1, 1 },
     "or3", "or3", SYN (5), FMT (3), 0x80e00000,
     & fmt_3_or3_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* or3 $dr,$sr,$ulo16 */
   {
     { 1, 1, 1, 1 },
     "or3.a", "or3", SYN (6), FMT (3), 0x80e00000,
     & fmt_3_or3_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* xor $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "xor", "xor", SYN (0), FMT (0), 0xd0,
     & fmt_0_add_ops[0],
-    { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* xor3 $dr,$sr,#$uimm16 */
   {
     { 1, 1, 1, 1 },
     "xor3", "xor3", SYN (3), FMT (2), 0x80d00000,
     & fmt_2_and3_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* xor3 $dr,$sr,$uimm16 */
   {
     { 1, 1, 1, 1 },
     "xor3.a", "xor3", SYN (4), FMT (2), 0x80d00000,
     & fmt_2_and3_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* addi $dr,#$simm8 */
   {
     { 1, 1, 1, 1 },
     "addi", "addi", SYN (7), FMT (4), 0x4000,
     & fmt_4_addi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* addi $dr,$simm8 */
   {
     { 1, 1, 1, 1 },
     "addi.a", "addi", SYN (8), FMT (4), 0x4000,
     & fmt_4_addi_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* addv $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "addv", "addv", SYN (0), FMT (5), 0x80,
     & fmt_5_addv_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* addv3 $dr,$sr,#$simm16 */
   {
     { 1, 1, 1, 1 },
     "addv3", "addv3", SYN (9), FMT (6), 0x80800000,
     & fmt_6_addv3_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* addv3 $dr,$sr,$simm16 */
   {
     { 1, 1, 1, 1 },
     "addv3.a", "addv3", SYN (10), FMT (6), 0x80800000,
     & fmt_6_addv3_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* addx $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "addx", "addx", SYN (0), FMT (7), 0x90,
     & fmt_7_addx_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* bc $disp8 */
   {
     { 1, 1, 1, 1 },
     "bc8", "bc", SYN (11), FMT (8), 0x7c00,
     & fmt_8_bc8_ops[0],
-    { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bc.s $disp8 */
   {
     { 1, 1, 1, 1 },
     "bc8.s", "bc.s", SYN (11), FMT (9), 0x7c00,
     0,
-    { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bc $disp24 */
   {
     { 1, 1, 1, 1 },
     "bc24", "bc", SYN (12), FMT (10), 0xfc000000,
     & fmt_10_bc24_ops[0],
-    { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bc.l $disp24 */
   {
     { 1, 1, 1, 1 },
     "bc24.l", "bc.l", SYN (12), FMT (11), 0xfc000000,
     0,
-    { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* beq $src1,$src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "beq", "beq", SYN (13), FMT (12), 0xb0000000,
     & fmt_12_beq_ops[0],
-    { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* beqz $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "beqz", "beqz", SYN (14), FMT (13), 0xb0800000,
     & fmt_13_beqz_ops[0],
-    { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bgez $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bgez", "bgez", SYN (14), FMT (13), 0xb0b00000,
     & fmt_13_beqz_ops[0],
-    { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bgtz $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bgtz", "bgtz", SYN (14), FMT (13), 0xb0d00000,
     & fmt_13_beqz_ops[0],
-    { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* blez $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "blez", "blez", SYN (14), FMT (13), 0xb0c00000,
     & fmt_13_beqz_ops[0],
-    { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bltz $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bltz", "bltz", SYN (14), FMT (13), 0xb0a00000,
     & fmt_13_beqz_ops[0],
-    { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bnez $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bnez", "bnez", SYN (14), FMT (13), 0xb0900000,
     & fmt_13_beqz_ops[0],
-    { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bl $disp8 */
   {
     { 1, 1, 1, 1 },
     "bl8", "bl", SYN (11), FMT (14), 0x7e00,
     & fmt_14_bl8_ops[0],
-    { 4, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bl.s $disp8 */
   {
     { 1, 1, 1, 1 },
     "bl8.s", "bl.s", SYN (11), FMT (9), 0x7e00,
     0,
-    { 4, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bl $disp24 */
   {
     { 1, 1, 1, 1 },
     "bl24", "bl", SYN (12), FMT (15), 0xfe000000,
     & fmt_15_bl24_ops[0],
-    { 4, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bl.l $disp24 */
   {
     { 1, 1, 1, 1 },
     "bl24.l", "bl.l", SYN (12), FMT (11), 0xfe000000,
     0,
-    { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* start-sanitize-m32rx */
 /* bcl $disp8 */
@@ -1443,7 +1427,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bcl8", "bcl", SYN (11), FMT (16), 0x7800,
     & fmt_16_bcl8_ops[0],
-    { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1452,7 +1436,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bcl8.s", "bcl.s", SYN (11), FMT (9), 0x7800,
     0,
-    { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1461,7 +1445,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bcl24", "bcl", SYN (12), FMT (17), 0xf8000000,
     & fmt_17_bcl24_ops[0],
-    { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1470,7 +1454,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bcl24.l", "bcl.l", SYN (12), FMT (11), 0xf8000000,
     0,
-    { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* bnc $disp8 */
@@ -1478,63 +1462,63 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bnc8", "bnc", SYN (11), FMT (8), 0x7d00,
     & fmt_8_bc8_ops[0],
-    { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bnc.s $disp8 */
   {
     { 1, 1, 1, 1 },
     "bnc8.s", "bnc.s", SYN (11), FMT (9), 0x7d00,
     0,
-    { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bnc $disp24 */
   {
     { 1, 1, 1, 1 },
     "bnc24", "bnc", SYN (12), FMT (10), 0xfd000000,
     & fmt_10_bc24_ops[0],
-    { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bnc.l $disp24 */
   {
     { 1, 1, 1, 1 },
     "bnc24.l", "bnc.l", SYN (12), FMT (11), 0xfd000000,
     0,
-    { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bne $src1,$src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bne", "bne", SYN (13), FMT (12), 0xb0100000,
     & fmt_12_beq_ops[0],
-    { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bra $disp8 */
   {
     { 1, 1, 1, 1 },
     "bra8", "bra", SYN (11), FMT (18), 0x7f00,
     & fmt_18_bra8_ops[0],
-    { 4, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bra.s $disp8 */
   {
     { 1, 1, 1, 1 },
     "bra8.s", "bra.s", SYN (11), FMT (9), 0x7f00,
     0,
-    { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bra $disp24 */
   {
     { 1, 1, 1, 1 },
     "bra24", "bra", SYN (12), FMT (19), 0xff000000,
     & fmt_19_bra24_ops[0],
-    { 4, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bra.l $disp24 */
   {
     { 1, 1, 1, 1 },
     "bra24.l", "bra.l", SYN (12), FMT (11), 0xff000000,
     0,
-    { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* start-sanitize-m32rx */
 /* bncl $disp8 */
@@ -1542,7 +1526,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bncl8", "bncl", SYN (11), FMT (16), 0x7900,
     & fmt_16_bcl8_ops[0],
-    { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1551,7 +1535,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bncl8.s", "bncl.s", SYN (11), FMT (9), 0x7900,
     0,
-    { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1560,7 +1544,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bncl24", "bncl", SYN (12), FMT (17), 0xf9000000,
     & fmt_17_bcl24_ops[0],
-    { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1569,7 +1553,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bncl24.l", "bncl.l", SYN (12), FMT (11), 0xf9000000,
     0,
-    { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* cmp $src1,$src2 */
@@ -1577,42 +1561,42 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "cmp", "cmp", SYN (15), FMT (20), 0x40,
     & fmt_20_cmp_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* cmpi $src2,#$simm16 */
   {
     { 1, 1, 1, 1 },
     "cmpi", "cmpi", SYN (16), FMT (21), 0x80400000,
     & fmt_21_cmpi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* cmpi $src2,$simm16 */
   {
     { 1, 1, 1, 1 },
     "cmpi.a", "cmpi", SYN (17), FMT (21), 0x80400000,
     & fmt_21_cmpi_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* cmpu $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "cmpu", "cmpu", SYN (15), FMT (20), 0x50,
     & fmt_20_cmp_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* cmpui $src2,#$uimm16 */
   {
     { 1, 1, 1, 1 },
     "cmpui", "cmpui", SYN (18), FMT (22), 0x80500000,
     & fmt_22_cmpui_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* cmpui $src2,$uimm16 */
   {
     { 1, 1, 1, 1 },
     "cmpui.a", "cmpui", SYN (19), FMT (22), 0x80500000,
     & fmt_22_cmpui_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* start-sanitize-m32rx */
 /* cmpeq $src1,$src2 */
@@ -1620,7 +1604,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "cmpeq", "cmpeq", SYN (15), FMT (20), 0x60,
     & fmt_20_cmp_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1629,7 +1613,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "cmpz", "cmpz", SYN (20), FMT (23), 0x70,
     & fmt_23_cmpz_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
 /* end-sanitize-m32rx */
 /* div $dr,$sr */
@@ -1637,28 +1621,28 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "div", "div", SYN (0), FMT (24), 0x90000000,
     & fmt_24_div_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* divu $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "divu", "divu", SYN (0), FMT (24), 0x90100000,
     & fmt_24_div_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* rem $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "rem", "rem", SYN (0), FMT (24), 0x90200000,
     & fmt_24_div_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* remu $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "remu", "remu", SYN (0), FMT (24), 0x90300000,
     & fmt_24_div_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* start-sanitize-m32rx */
 /* divh $dr,$sr */
@@ -1666,7 +1650,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "divh", "divh", SYN (0), FMT (24), 0x90000010,
     & fmt_24_div_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1675,7 +1659,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "jc", "jc", SYN (21), FMT (25), 0x1cc0,
     & fmt_25_jc_ops[0],
-    { 4, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1684,7 +1668,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "jnc", "jnc", SYN (21), FMT (25), 0x1dc0,
     & fmt_25_jc_ops[0],
-    { 4, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* jl $sr */
@@ -1692,231 +1676,231 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "jl", "jl", SYN (21), FMT (26), 0x1ec0,
     & fmt_26_jl_ops[0],
-    { 4, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
+    { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* jmp $sr */
   {
     { 1, 1, 1, 1 },
     "jmp", "jmp", SYN (21), FMT (27), 0x1fc0,
     & fmt_27_jmp_ops[0],
-    { 4, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* ld $dr,@$sr */
   {
     { 1, 1, 1, 1 },
     "ld", "ld", SYN (22), FMT (28), 0x20c0,
     & fmt_28_ld_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* ld $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
     "ld-2", "ld", SYN (23), FMT (29), 0x20c0,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* ld $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
     "ld-d", "ld", SYN (24), FMT (30), 0xa0c00000,
     & fmt_30_ld_d_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ld $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
     "ld-d2", "ld", SYN (25), FMT (31), 0xa0c00000,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldb $dr,@$sr */
   {
     { 1, 1, 1, 1 },
     "ldb", "ldb", SYN (22), FMT (32), 0x2080,
     & fmt_32_ldb_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* ldb $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
     "ldb-2", "ldb", SYN (23), FMT (29), 0x2080,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* ldb $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
     "ldb-d", "ldb", SYN (24), FMT (33), 0xa0800000,
     & fmt_33_ldb_d_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldb $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
     "ldb-d2", "ldb", SYN (25), FMT (31), 0xa0800000,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldh $dr,@$sr */
   {
     { 1, 1, 1, 1 },
     "ldh", "ldh", SYN (22), FMT (34), 0x20a0,
     & fmt_34_ldh_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* ldh $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
     "ldh-2", "ldh", SYN (23), FMT (29), 0x20a0,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* ldh $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
     "ldh-d", "ldh", SYN (24), FMT (35), 0xa0a00000,
     & fmt_35_ldh_d_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldh $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
     "ldh-d2", "ldh", SYN (25), FMT (31), 0xa0a00000,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldub $dr,@$sr */
   {
     { 1, 1, 1, 1 },
     "ldub", "ldub", SYN (22), FMT (32), 0x2090,
     & fmt_32_ldb_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* ldub $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
     "ldub-2", "ldub", SYN (23), FMT (29), 0x2090,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* ldub $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
     "ldub-d", "ldub", SYN (24), FMT (33), 0xa0900000,
     & fmt_33_ldb_d_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldub $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
     "ldub-d2", "ldub", SYN (25), FMT (31), 0xa0900000,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* lduh $dr,@$sr */
   {
     { 1, 1, 1, 1 },
     "lduh", "lduh", SYN (22), FMT (34), 0x20b0,
     & fmt_34_ldh_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* lduh $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
     "lduh-2", "lduh", SYN (23), FMT (29), 0x20b0,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* lduh $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
     "lduh-d", "lduh", SYN (24), FMT (35), 0xa0b00000,
     & fmt_35_ldh_d_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* lduh $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
     "lduh-d2", "lduh", SYN (25), FMT (31), 0xa0b00000,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ld $dr,@$sr+ */
   {
     { 1, 1, 1, 1 },
     "ld-plus", "ld", SYN (26), FMT (36), 0x20e0,
     & fmt_36_ld_plus_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* ld24 $dr,#$uimm24 */
   {
     { 1, 1, 1, 1 },
     "ld24", "ld24", SYN (27), FMT (37), 0xe0000000,
     & fmt_37_ld24_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ld24 $dr,$uimm24 */
   {
     { 1, 1, 1, 1 },
     "ld24.a", "ld24", SYN (28), FMT (37), 0xe0000000,
     & fmt_37_ld24_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldi $dr,#$simm8 */
   {
     { 1, 1, 1, 1 },
     "ldi8", "ldi", SYN (7), FMT (38), 0x6000,
     & fmt_38_ldi8_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* ldi $dr,$simm8 */
   {
     { 1, 1, 1, 1 },
     "ldi8.a", "ldi", SYN (8), FMT (38), 0x6000,
     & fmt_38_ldi8_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* ldi8 $dr,#$simm8 */
   {
     { 1, 1, 1, 1 },
     "ldi8a", "ldi8", SYN (7), FMT (38), 0x6000,
     & fmt_38_ldi8_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* ldi8 $dr,$simm8 */
   {
     { 1, 1, 1, 1 },
     "ldi8a.a", "ldi8", SYN (8), FMT (38), 0x6000,
     & fmt_38_ldi8_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* ldi $dr,$slo16 */
   {
     { 1, 1, 1, 1 },
     "ldi16", "ldi", SYN (29), FMT (39), 0x90f00000,
     & fmt_39_ldi16_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldi16 $dr,$slo16 */
   {
     { 1, 1, 1, 1 },
     "ldi16a", "ldi16", SYN (29), FMT (39), 0x90f00000,
     & fmt_39_ldi16_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* lock $dr,@$sr */
   {
     { 1, 1, 1, 1 },
     "lock", "lock", SYN (22), FMT (40), 0x20d0,
     & fmt_40_lock_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* machi $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "machi", "machi", SYN (15), FMT (41), 0x3040,
     & fmt_41_machi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* machi $src1,$src2,$acc */
@@ -1924,7 +1908,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "machi-a", "machi", SYN (30), FMT (42), 0x3040,
     & fmt_42_machi_a_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* maclo $src1,$src2 */
@@ -1932,7 +1916,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "maclo", "maclo", SYN (15), FMT (41), 0x3050,
     & fmt_41_machi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* maclo $src1,$src2,$acc */
@@ -1940,7 +1924,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "maclo-a", "maclo", SYN (30), FMT (42), 0x3050,
     & fmt_42_machi_a_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* macwhi $src1,$src2 */
@@ -1948,28 +1932,28 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "macwhi", "macwhi", SYN (15), FMT (41), 0x3060,
     & fmt_41_machi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* macwlo $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "macwlo", "macwlo", SYN (15), FMT (41), 0x3070,
     & fmt_41_machi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* mul $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "mul", "mul", SYN (0), FMT (0), 0x1060,
     & fmt_0_add_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* mulhi $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "mulhi", "mulhi", SYN (15), FMT (43), 0x3000,
     & fmt_43_mulhi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mulhi $src1,$src2,$acc */
@@ -1977,7 +1961,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mulhi-a", "mulhi", SYN (30), FMT (44), 0x3000,
     & fmt_44_mulhi_a_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mullo $src1,$src2 */
@@ -1985,7 +1969,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mullo", "mullo", SYN (15), FMT (43), 0x3010,
     & fmt_43_mulhi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mullo $src1,$src2,$acc */
@@ -1993,7 +1977,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mullo-a", "mullo", SYN (30), FMT (44), 0x3010,
     & fmt_44_mulhi_a_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mulwhi $src1,$src2 */
@@ -2001,28 +1985,28 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mulwhi", "mulwhi", SYN (15), FMT (43), 0x3020,
     & fmt_43_mulhi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* mulwlo $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "mulwlo", "mulwlo", SYN (15), FMT (43), 0x3030,
     & fmt_43_mulhi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* mv $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "mv", "mv", SYN (0), FMT (45), 0x1080,
     & fmt_45_mv_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* mvfachi $dr */
   {
     { 1, 1, 1, 1 },
     "mvfachi", "mvfachi", SYN (31), FMT (46), 0x50f0,
     & fmt_46_mvfachi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mvfachi $dr,$accs */
@@ -2030,7 +2014,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvfachi-a", "mvfachi", SYN (32), FMT (47), 0x50f0,
     & fmt_47_mvfachi_a_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mvfaclo $dr */
@@ -2038,7 +2022,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvfaclo", "mvfaclo", SYN (31), FMT (46), 0x50f1,
     & fmt_46_mvfachi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mvfaclo $dr,$accs */
@@ -2046,7 +2030,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvfaclo-a", "mvfaclo", SYN (32), FMT (47), 0x50f1,
     & fmt_47_mvfachi_a_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mvfacmi $dr */
@@ -2054,7 +2038,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvfacmi", "mvfacmi", SYN (31), FMT (46), 0x50f2,
     & fmt_46_mvfachi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mvfacmi $dr,$accs */
@@ -2062,7 +2046,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvfacmi-a", "mvfacmi", SYN (32), FMT (47), 0x50f2,
     & fmt_47_mvfachi_a_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mvfc $dr,$scr */
@@ -2070,14 +2054,14 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvfc", "mvfc", SYN (33), FMT (48), 0x1090,
     & fmt_48_mvfc_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* mvtachi $src1 */
   {
     { 1, 1, 1, 1 },
     "mvtachi", "mvtachi", SYN (34), FMT (49), 0x5070,
     & fmt_49_mvtachi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mvtachi $src1,$accs */
@@ -2085,7 +2069,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvtachi-a", "mvtachi", SYN (35), FMT (50), 0x5070,
     & fmt_50_mvtachi_a_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mvtaclo $src1 */
@@ -2093,7 +2077,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvtaclo", "mvtaclo", SYN (34), FMT (49), 0x5071,
     & fmt_49_mvtachi_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mvtaclo $src1,$accs */
@@ -2101,7 +2085,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvtaclo-a", "mvtaclo", SYN (35), FMT (50), 0x5071,
     & fmt_50_mvtachi_a_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mvtc $sr,$dcr */
@@ -2109,35 +2093,35 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvtc", "mvtc", SYN (36), FMT (51), 0x10a0,
     & fmt_51_mvtc_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* neg $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "neg", "neg", SYN (0), FMT (45), 0x30,
     & fmt_45_mv_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* nop */
   {
     { 1, 1, 1, 1 },
     "nop", "nop", SYN (37), FMT (52), 0x7000,
     0,
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* not $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "not", "not", SYN (0), FMT (45), 0xb0,
     & fmt_45_mv_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* rac */
   {
     { 1, 1, 1, 1 },
     "rac", "rac", SYN (37), FMT (53), 0x5090,
     & fmt_53_rac_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* rac $accd */
@@ -2145,7 +2129,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "rac-d", "rac", SYN (38), FMT (54), 0x5090,
     & fmt_54_rac_d_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2154,7 +2138,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "rac-ds", "rac", SYN (39), FMT (55), 0x5090,
     & fmt_55_rac_ds_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2163,7 +2147,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "rac-dsi", "rac", SYN (40), FMT (56), 0x5090,
     & fmt_56_rac_dsi_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* rach */
@@ -2171,7 +2155,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "rach", "rach", SYN (37), FMT (53), 0x5080,
     & fmt_53_rac_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* rach $accd */
@@ -2179,7 +2163,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "rach-d", "rach", SYN (38), FMT (54), 0x5080,
     & fmt_54_rac_d_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2188,7 +2172,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "rach-ds", "rach", SYN (39), FMT (55), 0x5080,
     & fmt_55_rac_ds_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2197,7 +2181,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "rach-dsi", "rach", SYN (40), FMT (56), 0x5080,
     & fmt_56_rac_dsi_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* rte */
@@ -2205,280 +2189,280 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "rte", "rte", SYN (37), FMT (57), 0x10d6,
     & fmt_57_rte_ops[0],
-    { 4, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* seth $dr,#$hi16 */
   {
     { 1, 1, 1, 1 },
     "seth", "seth", SYN (41), FMT (58), 0xd0c00000,
     & fmt_58_seth_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* seth $dr,$hi16 */
   {
     { 1, 1, 1, 1 },
     "seth.a", "seth", SYN (42), FMT (58), 0xd0c00000,
     & fmt_58_seth_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* sll $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "sll", "sll", SYN (0), FMT (0), 0x1040,
     & fmt_0_add_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* sll3 $dr,$sr,#$simm16 */
   {
     { 1, 1, 1, 1 },
     "sll3", "sll3", SYN (9), FMT (59), 0x90c00000,
     & fmt_59_sll3_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* sll3 $dr,$sr,$simm16 */
   {
     { 1, 1, 1, 1 },
     "sll3.a", "sll3", SYN (10), FMT (59), 0x90c00000,
     & fmt_59_sll3_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* slli $dr,#$uimm5 */
   {
     { 1, 1, 1, 1 },
     "slli", "slli", SYN (43), FMT (60), 0x5040,
     & fmt_60_slli_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* slli $dr,$uimm5 */
   {
     { 1, 1, 1, 1 },
     "slli.a", "slli", SYN (44), FMT (60), 0x5040,
     & fmt_60_slli_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* sra $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "sra", "sra", SYN (0), FMT (0), 0x1020,
     & fmt_0_add_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* sra3 $dr,$sr,#$simm16 */
   {
     { 1, 1, 1, 1 },
     "sra3", "sra3", SYN (9), FMT (59), 0x90a00000,
     & fmt_59_sll3_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* sra3 $dr,$sr,$simm16 */
   {
     { 1, 1, 1, 1 },
     "sra3.a", "sra3", SYN (10), FMT (59), 0x90a00000,
     & fmt_59_sll3_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* srai $dr,#$uimm5 */
   {
     { 1, 1, 1, 1 },
     "srai", "srai", SYN (43), FMT (60), 0x5020,
     & fmt_60_slli_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* srai $dr,$uimm5 */
   {
     { 1, 1, 1, 1 },
     "srai.a", "srai", SYN (44), FMT (60), 0x5020,
     & fmt_60_slli_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* srl $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "srl", "srl", SYN (0), FMT (0), 0x1000,
     & fmt_0_add_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* srl3 $dr,$sr,#$simm16 */
   {
     { 1, 1, 1, 1 },
     "srl3", "srl3", SYN (9), FMT (59), 0x90800000,
     & fmt_59_sll3_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* srl3 $dr,$sr,$simm16 */
   {
     { 1, 1, 1, 1 },
     "srl3.a", "srl3", SYN (10), FMT (59), 0x90800000,
     & fmt_59_sll3_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* srli $dr,#$uimm5 */
   {
     { 1, 1, 1, 1 },
     "srli", "srli", SYN (43), FMT (60), 0x5000,
     & fmt_60_slli_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* srli $dr,$uimm5 */
   {
     { 1, 1, 1, 1 },
     "srli.a", "srli", SYN (44), FMT (60), 0x5000,
     & fmt_60_slli_ops[0],
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* st $src1,@$src2 */
   {
     { 1, 1, 1, 1 },
     "st", "st", SYN (45), FMT (61), 0x2040,
     & fmt_61_st_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* st $src1,@($src2) */
   {
     { 1, 1, 1, 1 },
     "st-2", "st", SYN (46), FMT (62), 0x2040,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* st $src1,@($slo16,$src2) */
   {
     { 1, 1, 1, 1 },
     "st-d", "st", SYN (47), FMT (63), 0xa0400000,
     & fmt_63_st_d_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* st $src1,@($src2,$slo16) */
   {
     { 1, 1, 1, 1 },
     "st-d2", "st", SYN (48), FMT (64), 0xa0400000,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* stb $src1,@$src2 */
   {
     { 1, 1, 1, 1 },
     "stb", "stb", SYN (45), FMT (65), 0x2000,
     & fmt_65_stb_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* stb $src1,@($src2) */
   {
     { 1, 1, 1, 1 },
     "stb-2", "stb", SYN (46), FMT (62), 0x2000,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* stb $src1,@($slo16,$src2) */
   {
     { 1, 1, 1, 1 },
     "stb-d", "stb", SYN (47), FMT (66), 0xa0000000,
     & fmt_66_stb_d_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* stb $src1,@($src2,$slo16) */
   {
     { 1, 1, 1, 1 },
     "stb-d2", "stb", SYN (48), FMT (64), 0xa0000000,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* sth $src1,@$src2 */
   {
     { 1, 1, 1, 1 },
     "sth", "sth", SYN (45), FMT (67), 0x2020,
     & fmt_67_sth_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* sth $src1,@($src2) */
   {
     { 1, 1, 1, 1 },
     "sth-2", "sth", SYN (46), FMT (62), 0x2020,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* sth $src1,@($slo16,$src2) */
   {
     { 1, 1, 1, 1 },
     "sth-d", "sth", SYN (47), FMT (68), 0xa0200000,
     & fmt_68_sth_d_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* sth $src1,@($src2,$slo16) */
   {
     { 1, 1, 1, 1 },
     "sth-d2", "sth", SYN (48), FMT (64), 0xa0200000,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* st $src1,@+$src2 */
   {
     { 1, 1, 1, 1 },
     "st-plus", "st", SYN (49), FMT (69), 0x2060,
     & fmt_69_st_plus_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* st $src1,@-$src2 */
   {
     { 1, 1, 1, 1 },
     "st-minus", "st", SYN (50), FMT (69), 0x2070,
     & fmt_69_st_plus_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* sub $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "sub", "sub", SYN (0), FMT (0), 0x20,
     & fmt_0_add_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* subv $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "subv", "subv", SYN (0), FMT (5), 0x0,
     & fmt_5_addv_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* subx $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "subx", "subx", SYN (0), FMT (7), 0x10,
     & fmt_7_addx_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* trap #$uimm4 */
   {
     { 1, 1, 1, 1 },
     "trap", "trap", SYN (51), FMT (70), 0x10f0,
     & fmt_70_trap_ops[0],
-    { 4, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* trap $uimm4 */
   {
     { 1, 1, 1, 1 },
     "trap.a", "trap", SYN (52), FMT (70), 0x10f0,
     & fmt_70_trap_ops[0],
-    { 4, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* unlock $src1,@$src2 */
   {
     { 1, 1, 1, 1 },
     "unlock", "unlock", SYN (45), FMT (71), 0x2050,
     & fmt_71_unlock_ops[0],
-    { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* push $src1 */
   {
     { 1, 1, 1, 1 },
     "push", "push", SYN (34), FMT (72), 0x207f,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* pop $dr */
   {
     { 1, 1, 1, 1 },
     "pop", "pop", SYN (31), FMT (73), 0x20ef,
     0,
-    { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* start-sanitize-m32rx */
 /* satb $dr,$src2 */
@@ -2486,7 +2470,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "satb", "satb", SYN (53), FMT (74), 0x80000100,
     & fmt_74_satb_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2495,7 +2479,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "sath", "sath", SYN (53), FMT (74), 0x80000200,
     & fmt_74_satb_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2504,7 +2488,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "sat", "sat", SYN (53), FMT (75), 0x80000000,
     & fmt_75_sat_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2513,7 +2497,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "pcmpbz", "pcmpbz", SYN (20), FMT (23), 0x370,
     & fmt_23_cmpz_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2522,7 +2506,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "sadd", "sadd", SYN (37), FMT (76), 0x50e4,
     & fmt_76_sadd_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2531,7 +2515,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "macwu1", "macwu1", SYN (15), FMT (77), 0x50b0,
     & fmt_77_macwu1_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2540,7 +2524,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "msblo", "msblo", SYN (15), FMT (41), 0x50d0,
     & fmt_41_machi_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2549,7 +2533,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mulwu1", "mulwu1", SYN (15), FMT (78), 0x50a0,
     & fmt_78_mulwu1_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2558,7 +2542,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "maclh1", "maclh1", SYN (15), FMT (77), 0x50c0,
     & fmt_77_macwu1_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2567,7 +2551,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "sc", "sc", SYN (37), FMT (79), 0x7401,
     & fmt_79_sc_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2576,7 +2560,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "snc", "snc", SYN (37), FMT (79), 0x7501,
     & fmt_79_sc_ops[0],
-    { 4, 0, { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+    { 2, 0, { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 };
diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index 90c913c..8adf49e 100644
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -107,16 +107,6 @@ typedef enum mach_attr {
  , MACH_MAX
 } MACH_ATTR;
 
-/* Enum declaration for instructions which modify the link register as a side effect.  */
-typedef enum write_lr_attr {
-  WRITE_LR_NO, WRITE_LR_YES
-} WRITE_LR_ATTR;
-
-/* Enum declaration for instructions which modify their source register as a side effect.  */
-typedef enum write_src_attr {
-  WRITE_SRC_NO, WRITE_SRC_YES
-} WRITE_SRC_ATTR;
-
 /* start-sanitize-m32rx */
 /* Enum declaration for parallel execution pipeline selection.  */
 typedef enum pipe_attr {
@@ -151,9 +141,8 @@ typedef enum cgen_insn_attr {
 /* start-sanitize-m32rx */
  , CGEN_INSN_PIPE
 /* end-sanitize-m32rx */
- , CGEN_INSN_WRITE_LR, CGEN_INSN_WRITE_SRC, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI
- , CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE
- , CGEN_INSN_UNCOND_CTI
+ , CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL
+ , CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
 } CGEN_INSN_ATTR;
 
 /* Number of non-boolean elements in cgen_insn.  */