From: Eric Anholt <eric@anholt.net>
Date: Tue, 19 Oct 2010 21:50:42 +0000 (-0700)
Subject: i965: Set the source operand types for gen6 if/else/endif to integer.
X-Git-Tag: mesa-7.10~1098
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6ea108e7db79cb7135a8a1ef216e25381f72c225;p=platform%2Fupstream%2Fmesa.git

i965: Set the source operand types for gen6 if/else/endif to integer.

I don't think this should matter, but I'm not sure, and it's
recommended by a kernel checker in fulsim.
---

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 7348924..399b99c 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -832,8 +832,8 @@ struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size)
    } else {
       brw_set_dest(insn, brw_imm_w(0));
       insn->bits1.branch_gen6.jump_count = 0;
-      brw_set_src0(insn, brw_null_reg());
-      brw_set_src1(insn, brw_null_reg());
+      brw_set_src0(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+      brw_set_src1(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
    }
 
    insn->header.execution_size = execute_size;
@@ -897,8 +897,8 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
    } else {
       brw_set_dest(insn, brw_imm_w(0));
       insn->bits1.branch_gen6.jump_count = 0;
-      brw_set_src0(insn, brw_null_reg());
-      brw_set_src1(insn, brw_null_reg());
+      brw_set_src0(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+      brw_set_src1(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
    }
 
    insn->header.compression_control = BRW_COMPRESSION_NONE;
@@ -956,8 +956,8 @@ void brw_ENDIF(struct brw_compile *p,
 	 brw_set_src1(insn, brw_imm_d(0x0));
       } else {
 	 brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_W));
-	 brw_set_src0(insn, brw_null_reg());
-	 brw_set_src1(insn, brw_null_reg());
+	 brw_set_src0(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+	 brw_set_src1(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
       }
 
       insn->header.compression_control = BRW_COMPRESSION_NONE;