From: Simon Atanasyan Date: Sat, 13 Jun 2015 14:48:14 +0000 (+0000) Subject: [Mips] Support R_MIPS_PC16 relocation handling X-Git-Tag: llvmorg-3.7.0-rc1~2420 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6df6c75b61405f6a8576c863f43a73f865473846;p=platform%2Fupstream%2Fllvm.git [Mips] Support R_MIPS_PC16 relocation handling llvm-svn: 239677 --- diff --git a/lld/lib/ReaderWriter/ELF/Mips/MipsRelocationHandler.cpp b/lld/lib/ReaderWriter/ELF/Mips/MipsRelocationHandler.cpp index 0a4a452..227465e 100644 --- a/lld/lib/ReaderWriter/ELF/Mips/MipsRelocationHandler.cpp +++ b/lld/lib/ReaderWriter/ELF/Mips/MipsRelocationHandler.cpp @@ -87,6 +87,8 @@ static MipsRelocationParams getRelocationParams(uint32_t rType) { case R_MIPS_26: case LLD_R_MIPS_GLOBAL_26: return {4, 0x3ffffff, 2, false, dummyCheck}; + case R_MIPS_PC16: + return {4, 0xffff, 2, false, signedCheck<18>}; case R_MIPS_PC18_S3: return {4, 0x3ffff, 3, false, signedCheck<21>}; case R_MIPS_PC19_S2: @@ -295,6 +297,15 @@ static int64_t relocGPRel32(uint64_t S, int64_t A, uint64_t GP) { return A + S - GP; } +/// \brief R_MIPS_PC16 +/// local/external: (S + A - P) >> 2 +static ErrorOr relocPc16(uint64_t P, uint64_t S, int64_t A) { + A = llvm::SignExtend32<18>(A); + if ((S + A) & 3) + return make_unaligned_range_reloc_error(); + return S + A - P; +} + /// \brief R_MIPS_PC18_S3, R_MICROMIPS_PC18_S3 /// local/external: (S + A - P) >> 3 (P with cleared 3 less significant bits) static ErrorOr relocPc18(uint64_t P, uint64_t S, int64_t A) { @@ -344,7 +355,7 @@ static int32_t relocPc10(uint64_t P, uint64_t S, int64_t A) { } /// \brief R_MICROMIPS_PC16_S1 -static int32_t relocPc16(uint64_t P, uint64_t S, int64_t A) { +static int32_t relocPc16Micro(uint64_t P, uint64_t S, int64_t A) { A = llvm::SignExtend32<17>(A); return S + A - P; } @@ -489,6 +500,8 @@ static ErrorOr calculateRelocation(Reference::KindValue kind, case R_MIPS_GOT_OFST: case R_MICROMIPS_GOT_OFST: return relocGOTOfst(tgtAddr, addend); + case R_MIPS_PC16: + return relocPc16(relAddr, tgtAddr, addend); case R_MIPS_PC18_S3: case R_MICROMIPS_PC18_S3: return relocPc18(relAddr, tgtAddr, addend); @@ -506,7 +519,7 @@ static ErrorOr calculateRelocation(Reference::KindValue kind, case R_MICROMIPS_PC10_S1: return relocPc10(relAddr, tgtAddr, addend); case R_MICROMIPS_PC16_S1: - return relocPc16(relAddr, tgtAddr, addend); + return relocPc16Micro(relAddr, tgtAddr, addend); case R_MICROMIPS_PC23_S2: return relocPc23(relAddr, tgtAddr, addend); case R_MIPS_TLS_DTPREL_HI16: diff --git a/lld/test/elf/Mips/rel-pc16-align.test b/lld/test/elf/Mips/rel-pc16-align.test new file mode 100644 index 0000000..6a0e61d --- /dev/null +++ b/lld/test/elf/Mips/rel-pc16-align.test @@ -0,0 +1,43 @@ +# Check incorrect alignment handling for R_MIPS_PC16 relocation. + +# RUN: yaml2obj -format=elf %s > %t.o +# RUN: not lld -flavor gnu -target mipsel -e T0 -o %t.exe %t.o 2>&1 \ +# RUN: | FileCheck %s + +# CHECK: Relocation not aligned in file {{.*}} reference from T0+0 to T1+0 of type 10 (R_MIPS_PC16) + +FileHeader: + Class: ELFCLASS32 + Data: ELFDATA2LSB + Type: ET_REL + Machine: EM_MIPS + Flags: [EF_MIPS_CPIC, EF_MIPS_ABI_O32, EF_MIPS_ARCH_32] + +Sections: +- Name: .text + Type: SHT_PROGBITS + Size: 8 + AddressAlign: 16 + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + +- Name: .rel.text + Type: SHT_REL + Info: .text + AddressAlign: 4 + Relocations: + - Offset: 0 + Symbol: T1 + Type: R_MIPS_PC16 + +Symbols: + Global: + - Name: T0 + Section: .text + Type: STT_FUNC + Value: 0 + Size: 8 + - Name: T1 + Section: .text + Type: STT_FUNC + Value: 6 + Size: 2 diff --git a/lld/test/elf/Mips/rel-pc16-overflow.test b/lld/test/elf/Mips/rel-pc16-overflow.test new file mode 100644 index 0000000..d1844b6 --- /dev/null +++ b/lld/test/elf/Mips/rel-pc16-overflow.test @@ -0,0 +1,45 @@ +# Check R_MIPS_PC16 relocation overflow handling. + +# RUN: yaml2obj -format=elf %s > %t.o +# RUN: not lld -flavor gnu -target mipsel -e T0 -o %t.exe %t.o 2>&1 \ +# RUN: | FileCheck %s + +# CHECK: Relocation out of range in file {{.*}} reference from T0+0 to T1+131068 of type 10 (R_MIPS_PC16) + +FileHeader: + Class: ELFCLASS32 + Data: ELFDATA2LSB + Type: ET_REL + Machine: EM_MIPS + Flags: [EF_MIPS_CPIC, EF_MIPS_ABI_O32, EF_MIPS_ARCH_32] + +Sections: +- Name: .text + Type: SHT_PROGBITS + Content: "ff7f00000000000000000000" +# ^ T1 +# ^ T0 A := 0x7fff << 2 = 0x1fffc + AddressAlign: 16 + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + +- Name: .rel.text + Type: SHT_REL + Info: .text + AddressAlign: 4 + Relocations: + - Offset: 0 + Symbol: T1 + Type: R_MIPS_PC16 + +Symbols: + Global: + - Name: T0 + Section: .text + Type: STT_FUNC + Value: 0 + Size: 8 + - Name: T1 + Section: .text + Type: STT_FUNC + Value: 8 + Size: 4 diff --git a/lld/test/elf/Mips/rel-pc16.test b/lld/test/elf/Mips/rel-pc16.test new file mode 100644 index 0000000..903e234 --- /dev/null +++ b/lld/test/elf/Mips/rel-pc16.test @@ -0,0 +1,53 @@ +# Check handling of R_MIPS_PC16 relocation. + +# RUN: yaml2obj -format=elf %s > %t.o +# RUN: lld -flavor gnu -target mipsel -e T0 -o %t.exe %t.o +# RUN: llvm-objdump -s -t %t.exe | FileCheck %s + +# CHECK: Contents of section .text: +# CHECK-NEXT: {{[0-9A-F]+}} feff0000 00000000 00000000 +# ^ V +# A = -16 => +# V = (T1 - 16 - T0) >> 2 = -2 + +# CHECK: SYMBOL TABLE: +# CHECK: {{[0-9A-F]+}} g F .text 00000008 T0 +# CHECK: {{[0-9A-F]+}} g F .text 00000004 T1 + +FileHeader: + Class: ELFCLASS32 + Data: ELFDATA2LSB + Type: ET_REL + Machine: EM_MIPS + Flags: [EF_MIPS_CPIC, EF_MIPS_ABI_O32, EF_MIPS_ARCH_32] + +Sections: +- Name: .text + Type: SHT_PROGBITS + Content: "fcff00000000000000000000" +# ^ T1 +# ^ T0 A := 0xfffc << 2 = -16 + AddressAlign: 16 + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + +- Name: .rel.text + Type: SHT_REL + Info: .text + AddressAlign: 4 + Relocations: + - Offset: 0 + Symbol: T1 + Type: R_MIPS_PC16 + +Symbols: + Global: + - Name: T0 + Section: .text + Type: STT_FUNC + Value: 0 + Size: 8 + - Name: T1 + Section: .text + Type: STT_FUNC + Value: 8 + Size: 4