From: Vineet Gupta <vgupta@synopsys.com>
Date: Mon, 3 Aug 2015 12:57:56 +0000 (+0530)
Subject: ARCv2: [axs103_smp] Reduce clk for Quad FPGA configs
X-Git-Tag: v4.14-rc1~4918^2~8
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6de7abfbad1c6a45893a47a17c2ac91b551aa90d;p=platform%2Fkernel%2Flinux-rpi.git

ARCv2: [axs103_smp] Reduce clk for Quad FPGA configs

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
---

diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index 99f7da5..e7769c3 100644
--- a/arch/arc/plat-axs10x/axs10x.c
+++ b/arch/arc/plat-axs10x/axs10x.c
@@ -389,6 +389,21 @@ axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od)
 
 static void __init axs103_early_init(void)
 {
+	/*
+	 * AXS103 configurations for SMP/QUAD configurations share device tree
+	 * which defaults to 90 MHz. However recent failures of Quad config
+	 * revealed P&R timing violations so clamp it down to safe 50 MHz
+	 * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
+	 *
+	 * This hack is really hacky as of now. Fix it properly by getting the
+	 * number of cores as return value of platform's early SMP callback
+	 */
+#ifdef CONFIG_ARC_MCIP
+	unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
+	if (num_cores > 2)
+		arc_set_core_freq(50 * 1000000);
+#endif
+
 	switch (arc_get_core_freq()/1000000) {
 	case 33:
 		axs103_set_freq(1, 1, 1);