From: Minkyu Kang Date: Fri, 22 Jan 2010 02:41:50 +0000 (+0900) Subject: s5pc1xx: p1p2: add board files X-Git-Tag: JA08_20100122~11 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6de71cc45613366d1f2cfb6ca1d032cd0d8f4be6;p=kernel%2Fu-boot.git s5pc1xx: p1p2: add board files Signed-off-by: Minkyu Kang --- diff --git a/board/samsung/p1p2/Makefile b/board/samsung/p1p2/Makefile new file mode 100644 index 0000000..515e80e --- /dev/null +++ b/board/samsung/p1p2/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2009 +# Kyungmin Park, Samsung Electronics +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := p1p2.o onenand.o +SOBJS := lowlevel_init.o + +COBJS-$(CONFIG_S5PC110_MODEM) += modem_boot.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(SOBJS) $(OBJS) + $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/samsung/p1p2/config.mk b/board/samsung/p1p2/config.mk new file mode 100644 index 0000000..ebab420 --- /dev/null +++ b/board/samsung/p1p2/config.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2008 # Samsung Elecgtronics +# Kyungmin Park +# + +# On S5PC100 we use the 128 MiB OneDRAM bank at +# +# 0x30000000 to 0x35000000 (80MiB) +# 0x38000000 to 0x40000000 (128MiB) +# +# On S5PC110 we use the 128 MiB OneDRAM bank at +# +# 0x30000000 to 0x35000000 (80MiB) +# 0x40000000 to 0x48000000 (128MiB) +# +TEXT_BASE = 0x34800000 diff --git a/board/samsung/p1p2/lowlevel_init.S b/board/samsung/p1p2/lowlevel_init.S new file mode 100644 index 0000000..c914261 --- /dev/null +++ b/board/samsung/p1p2/lowlevel_init.S @@ -0,0 +1,516 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 2009 Samsung Electronics + * Kyungmin Park + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define DEBUG_PM_C110 +#undef DEBUG_PM_C110 + +/* + * Register usages: + * + * r5 has zero always + * r7 has S5PC100 GPIO base, 0xE0300000 + * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively + * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on + */ + +_TEXT_BASE: + .word TEXT_BASE + + .globl lowlevel_init +lowlevel_init: + mov r11, lr + + /* r5 has always zero */ + mov r5, #0 + + ldr r7, =S5PC100_GPIO_BASE + ldr r8, =S5PC100_GPIO_BASE + /* Read CPU ID */ + ldr r2, =S5PC1XX_PRO_ID + ldr r0, [r2] + mov r1, #0x00010000 + and r0, r0, r1 + cmp r0, r5 + beq 100f + ldr r8, =S5PC110_GPIO_BASE +100: + /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */ + cmp r7, r8 +#ifndef DEBUG_PM_C110 + addeq r0, r8, #0x280 @S5PC100_GPIO_J4_OFFSET + addne r0, r8, #0x2C0 @S5PC110_GPIO_J4_OFFSET + ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET + bic r1, r1, #(0xf << 4) @ 1 * 4-bit + orr r1, r1, #(0x1 << 4) + str r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET + + ldr r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET +#ifdef CONFIG_ONENAND_IPL + orr r1, r1, #(1 << 1) @ 1 * 1-bit +#else + bic r1, r1, #(1 << 1) +#endif + str r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET +#endif + + /* IO retension release */ + ldreq r0, =S5PC100_OTHERS @0xE0108200 + ldrne r0, =S5PC110_OTHERS @0xE010E000 + ldr r1, [r0] + ldreq r2, =(1 << 31) @IO_RET_REL + ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)) @ GPIO, UART_IO + orr r1, r1, r2 + str r1, [r0] + +#ifndef CONFIG_ONENAND_IPL + /* Disable Watchdog */ + ldreq r0, =S5PC100_WATCHDOG_BASE @0xEA200000 + ldrne r0, =S5PC110_WATCHDOG_BASE @0xE2700000 + str r5, [r0] + + /* setting SRAM */ + ldreq r0, =S5PC100_SROMC_BASE + ldrne r0, =S5PC110_SROMC_BASE + ldr r1, =0x9 + str r1, [r0] +#endif + + /* S5PC100 has 3 groups of interrupt sources */ + ldreq r0, =S5PC100_VIC0_BASE @0xE4000000 + ldrne r0, =S5PC110_VIC0_BASE @0xF2000000 + add r1, r0, #0x00100000 + add r2, r0, #0x00200000 + + /* Disable all interrupts (VIC0, VIC1 and VIC2) */ + mvn r3, #0x0 + str r3, [r0, #0x14] @INTENCLEAR + str r3, [r1, #0x14] @INTENCLEAR + str r3, [r2, #0x14] @INTENCLEAR + +#ifndef CONFIG_ONENAND_IPL + /* Set all interrupts as IRQ */ + str r5, [r0, #0xc] @INTSELECT + str r5, [r1, #0xc] @INTSELECT + str r5, [r2, #0xc] @INTSELECT + + /* Pending Interrupt Clear */ + str r5, [r0, #0xf00] @INTADDRESS + str r5, [r1, #0xf00] @INTADDRESS + str r5, [r2, #0xf00] @INTADDRESS +#endif + +#ifndef CONFIG_ONENAND_IPL + /* for UART */ + bl uart_asm_init + + bl internal_ram_init +#endif + +#ifdef CONFIG_ONENAND_IPL + /* init system clock */ + bl system_clock_init + + /* Board detection to set proper memory configuration */ + cmp r7, r8 + moveq r9, #1 /* r9 has 1Gib default at s5pc100 */ + movne r9, #2 /* r9 has 2Gib default at s5pc110 */ + /* FIXME 1Gib detection: Limo Universal */ + /* Check Limo Real board + * LR (suspend) LU J1B2 + * 0x04 0x01 (0x01) 0x01 (0x01) 0x01 (0x01) + * 0x24 0x28 (0xA8) 0x28 (0x6A) 0x1C (0x1C) + * 0x44 0x00 (0xC7) 0x00 (0x47) 0x00 (0x47) + * 0x64 0x03 (0x1F) 0x07 (0x1F) 0x0f (0x0F) + * + * Check (0 << 3) at 0x64 at boot + * Check 0x47 at 0x44 at suspend + */ + ldrne r2, =0xE0200C00 + ldrne r1, [r2, #0x64] + and r1, r1, #(1 << 2) + cmp r1, #(1 << 2) + moveq r9, #1 + ldr r1, [r2, #0x44] + cmp r1, #0x47 + moveq r9, #1 + /* + * Aquila Rev 0.5 : 4G3G1G x16 for Infineon ES3.1 + * Aquila Rev 0.6 : 4G1G1G x32 for MSM6290 + * Aquila Rev 0.7 : 4G2G1G x16 for Infineon ES3.1 + * Aquila Rev 0.8 : 4G3G1G x16 for Infineon ES3.1 + */ + ldr r2, =0xE0200200 + ldr r4, [r2, #0x48] + bic r1, r4, #(0xFF << 2) /* PULLUP_DISABLE: 4 * 2-bit */ + str r1, [r2, #0x48] + /* For write completion */ + nop + nop + + ldr r3, [r2, #0x44] + and r1, r3, #(0xf << 1) + cmp r1, #(0x5 << 2) + moveq r9, #3 + cmp r1, #(0x6 << 2) + moveq r9, #1 + cmp r1, #(0x7 << 2) + moveq r9, #2 + cmp r1, #(0x1 << 1) + moveq r9, #3 + str r4, [r2, #0x48] /* Restore PULLUP configuration */ + + bl mem_ctrl_asm_init + + /* OneNAND Sync Read Support at S5PC110 only + * RM[15] : Sync Read + * BRWL[14:12] : 7 CLK + * BL[11:9] : Continuous + * VHF[3] : Very High Frequency Enable (Over 83MHz) + * HF[2] : High Frequency Enable (Over 66MHz) + */ + cmp r7, r8 + ldrne r1, =0xE00C + + ldrne r0, =0xB001E442 + strneh r1, [r0] + + ldrne r0, =0xB0600000 + strne r1, [r0, #0x100] @ ONENAND_IF_CTRL + + /* Wakeup support. Don't know if it's going to be used, untested. */ + ldreq r0, =S5PC100_RST_STAT + ldrne r0, =S5PC110_RST_STAT + ldr r1, [r0] + biceq r1, r1, #0xfffffff7 + moveq r2, #(1 << 3) + bicne r1, r1, #0xfffeffff + movne r2, #(1 << 16) + cmp r1, r2 + bne 1f +wakeup: +#ifdef DEBUG_PM_C110 + mov r0, r8 + ldr r1, =0x22222222 + str r1, [r0, #0x0] @S5PC100_GPIO_A0_OFFSET + ldr r1, =0x00002222 + str r1, [r0, #0x20] @S5PC100_GPIO_A1_OFFSET + + /* UART_SEL MP0_5[7] at S5PC110 */ + add r0, r8, #0x360 @S5PC110_GPIO_MP0_5_OFFSET + ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET + bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit + orr r1, r1, #(0x1 << 28) @ Output + str r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET + + ldr r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET + bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit + orr r1, r1, #(0x2 << 14) @ Pull-up enabled + str r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET + + ldr r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET + orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit + str r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET + + ldr r0, =0xE2900000 @ S5PC110_PA_UART + orr r0, r0, #0x800 + mov r1, #0x3 + str r1, [r0, #0x000] @ ULCON + ldr r1, =0x245 + str r1, [r0, #0x004] @ UCON + mov r1, #0x23 + str r1, [r0, #0x028] @ UBRDIV + mov r1, #0x3 + str r1, [r0, #0x02C] @ UDIVSLOT + + mov r2, #'W' + strb r2, [r0, #0x020] @ UTXH +1001: + ldrb r3, [r0, #0x010] @ UTRSTAT + tst r3, #(1 << 2) + beq 1001b +#endif + + /* turn off L2 cache */ + bl l2_cache_disable + + cmp r7, r8 + ldreq r0, =0xC100 + ldrne r0, =0xC110 + + /* invalidate L2 cache also */ + bl invalidate_dcache + + /* turn on L2 cache */ + bl l2_cache_enable + + cmp r7, r8 + /* Load return address and jump to kernel */ + ldreq r0, =S5PC100_INFORM0 + ldrne r0, =S5PC110_INFORM0 + + /* r1 = physical address of s5pc1xx_cpu_resume function */ + ldr r1, [r0] + + /* Jump to kernel (sleep-s5pc1xx.S) */ + mov pc, r1 + nop + nop +#else + cmp r7, r8 + /* Clear wakeup status register */ + ldreq r0, =S5PC100_WAKEUP_STAT + ldrne r0, =S5PC110_WAKEUP_STAT + ldr r1, [r0] + str r1, [r0] +#endif +1: + mov lr, r11 + mov pc, lr + +/* + * system_clock_init: Initialize core clock and bus clock. + * void system_clock_init(void) + */ +system_clock_init: + ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + + /* Check S5PC100 */ + cmp r7, r8 + bne 110f +100: +#ifndef DEBUG_PM_C110 + /* Set Lock Time */ + ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 + str r1, [r0, #0x000] @ S5PC100_APLL_LOCK + str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK + str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK + str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK + + /* S5P_APLL_CON */ +#ifdef CONFIG_CLK_667_166_83 + ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz) +#elif defined(CONFIG_CLK_666_166_66) + ldr r1, =0x814d0301 @ SDIV 1, PDIV 3, MDIV 333 (1333MHz) +#elif defined(CONFIG_CLK_600_150_75) + ldr r1, =0x812C0300 @ SDIV 0, PDIV 3, MDIV 300 (1200MHz) +#elif defined(CONFIG_CLK_533_133_66) + ldr r1, =0x810b0300 @ SDIV 0, PDIV 3, MDIV 267 (1066MHz) +#elif defined(CONFIG_CLK_500_166_66) + ldr r1, =0x81f40301 @ SDIV 1, PDIV 3, MDIV 500 (1000MHz) +#elif defined(CONFIG_CLK_467_117_59) + ldr r1, =0x826E0401 @ SDIV 1, PDIV 4, MDIV 622 (933MHz) +#elif defined(CONFIG_CLK_400_100_50) + ldr r1, =0x81900301 @ SDIV 1, PDIV 3, MDIV 400 (800MHz) +#else +#error you should set the correct clock configuration +#endif + str r1, [r0, #0x100] + /* S5P_MPLL_CON */ + ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz) + str r1, [r0, #0x104] + /* S5P_EPLL_CON */ + ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz) + str r1, [r0, #0x108] + /* S5P_HPLL_CON */ + ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96 + str r1, [r0, #0x10C] + + ldr r1, [r0, #0x300] + ldr r2, =0x00003fff + bic r1, r1, r2 +#ifdef CONFIG_CLK_800_166_66 + ldr r2, =0x00011401 +#elif defined(CONFIG_CLK_500_166_66) + ldr r2, =0x00011201 +#elif defined(CONFIG_CLK_666_166_66) + ldr r2, =0x00011300 +#else + ldr r2, =0x00011301 +#endif + orr r1, r1, r2 + str r1, [r0, #0x300] + ldr r1, [r0, #0x304] + ldr r2, =0x00011110 + orr r1, r1, r2 + str r1, [r0, #0x304] + ldr r1, =0x00000001 + str r1, [r0, #0x308] + + /* Set Source Clock */ + ldr r1, =0x00001111 @ A, M, E, HPLL Muxing + str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0 +#endif + b 200f +110: + /* Set Clock divider */ + ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5 + str r1, [r0, #0x300] + ldr r1, =0x11110111 @ UART[3210]: MMC[3210] + str r1, [r0, #0x310] + + /* Set Lock Time */ + ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 + str r1, [r0, #0x000] @ S5PC110_APLL_LOCK + str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK + str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK + str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK + + /* S5PC110_APLL_CON */ + ldr r1, =0x80C80601 @ 800MHz + str r1, [r0, #0x100] + /* S5PC110_MPLL_CON */ + ldr r1, =0x829B0C01 @ 667MHz + str r1, [r0, #0x108] + /* S5PC110_EPLL_CON */ + ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2 + str r1, [r0, #0x110] + /* S5PC110_VPLL_CON */ + ldr r1, =0x806C0603 @ 54MHz + str r1, [r0, #0x120] + + /* Set Source Clock */ + ldr r1, =0x10001111 @ A, M, E, VPLL Muxing + str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0 + + /* OneDRAM(DMC0) clock setting */ + ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL + str r1, [r0, #0x218] @ S5PC110_CLK_SRC6 + ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1 + str r1, [r0, #0x318] @ S5PC110_CLK_DIV6 + + /* XCLKOUT = XUSBXTI 24MHz */ + add r2, r0, #0xE000 @ S5PC110_OTHERS + ldr r1, [r2] + orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI + str r1, [r2] + + /* CLK_IP0 */ + ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5] + str r1, [r0, #0x460] @ S5PC110_CLK_IP0 + + /* CLK_IP1 */ + ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16] + @ NANDXL[24] + str r1, [r0, #0x464] @ S5PC110_CLK_IP1 + + /* CLK_IP2 */ + ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9] + @ HOSTIF[10] HSMMC0[16] + @ HSMMC2[18] VIC[27:24] + str r1, [r0, #0x468] @ S5PC110_CLK_IP2 + + /* CLK_IP3 */ + ldr r1, =0x8edf038c @ I2C[8:6] + @ SYSTIMER[16] UART0[17] + @ UART1[18] UART2[19] + @ UART3[20] WDT[22] + @ PWM[23] GPIO[26] SYSCON[27] + str r1, [r0, #0x46c] @ S5PC110_CLK_IP3 + + /* CLK_IP4 */ + ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5] + str r1, [r0, #0x470] @ S5PC110_CLK_IP3 + +200: + /* wait at least 200us to stablize all clock */ + mov r2, #0x10000 +1: subs r2, r2, #1 + bne 1b + + mov pc, lr + +#ifndef CONFIG_ONENAND_IPL +internal_ram_init: + ldreq r0, =0xE3800000 + ldrne r0, =0xF1500000 + ldr r1, =0x0 + str r1, [r0] + + mov pc, lr +#endif + +#ifndef CONFIG_ONENAND_IPL +/* + * uart_asm_init: Initialize UART's pins + */ +uart_asm_init: + /* set GPIO to enable UART0-UART4 */ + mov r0, r8 + ldr r1, =0x22222222 + str r1, [r0, #0x0] @S5PC100_GPIO_A0_OFFSET + ldr r1, =0x00002222 + str r1, [r0, #0x20] @S5PC100_GPIO_A1_OFFSET + + /* Check S5PC100 */ + cmp r7, r8 + bne 110f + +#ifndef DEBUG_PM_C110 + /* UART_SEL GPK0[5] at S5PC100 */ + add r0, r8, #0x2A0 @S5PC100_GPIO_K0_OFFSET + ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET + bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit + orr r1, r1, #(0x1 << 20) @ Output + str r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET + + ldr r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET + bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit + orr r1, r1, #(0x2 << 10) @ Pull-up enabled + str r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET + + ldr r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET + orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit + str r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET +#endif + b 200f +110: + /* + * Note that the following address + * 0xE020'0360 is reserved address at S5PC100 + */ + /* UART_SEL MP0_5[7] at S5PC110 */ + add r0, r8, #0x360 @S5PC110_GPIO_MP0_5_OFFSET + ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET + bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit + orr r1, r1, #(0x1 << 28) @ Output + str r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET + + ldr r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET + bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit + orr r1, r1, #(0x2 << 14) @ Pull-up enabled + str r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET + + ldr r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET + orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit + str r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET +200: + mov pc, lr +#endif diff --git a/board/samsung/p1p2/mem_setup.S b/board/samsung/p1p2/mem_setup.S new file mode 100644 index 0000000..8fa61df --- /dev/null +++ b/board/samsung/p1p2/mem_setup.S @@ -0,0 +1,334 @@ +/* + * Copyright (C) 2009 Samsung Electrnoics + * Minkyu Kang + * Kyungmin Park + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define NEW_MEMORY_TIMING +#undef NEW_MEMORY_TIMING + + .globl mem_ctrl_asm_init +mem_ctrl_asm_init: + cmp r7, r8 + +#ifdef NEW_MEMORY_TIMING + /* CLOCK_POWER_BASE */ + ldrne r0, =0xE0100000 + orrne r0, r0, #0x6200 + orrne r0, r0, #0x0008 + ldrne r1, =0x00000000 @ 0 : SCLK_ONEDRAM, 1 : HCLK200 + strne r1, [r0] + + /* ASYNC_MSYS_DMC0_BASE */ + ldrne r0, =0xF1E00000 + ldrne r1, =0x0 + strne r1, [r0, #0x0] + ldrne r1, =0x0 + str r1, [r0, #0xC] +#endif + + ldreq r0, =S5PC100_DMC_BASE @ 0xE6000000 + ldrne r0, =S5PC110_DMC0_BASE @ 0xF0000000 + ldrne r6, =S5PC110_DMC1_BASE @ 0xF1400000 + + /* DLL parameter setting */ +#ifdef NEW_MEMORY_TIMING + ldr r1, =0x003B3B00 +#else + ldr r1, =0x50101000 +#endif + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET +#ifdef NEW_MEMORY_TIMING + ldr r1, =0x00000004 +#else + ldr r1, =0x000000f4 +#endif + str r1, [r0, #0x01C] @ PHYCONTROL1_OFFSET + strne r1, [r6, #0x01C] @ PHYCONTROL1_OFFSET + ldreq r1, =0x0 + streq r1, [r0, #0x020] @ PHYCONTROL2_OFFSET + + /* DLL on */ +#ifdef NEW_MEMORY_TIMING + ldr r1, =0x003B3B02 +#else + ldr r1, =0x50101002 +#endif + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + + /* DLL start */ +#ifdef NEW_MEMORY_TIMING + ldr r1, =0x003B3B03 +#else + ldr r1, =0x50101003 +#endif + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + + mov r2, #0x4000 +wait: subs r2, r2, #0x1 + cmp r2, #0x0 + bne wait + + cmp r7, r8 + /* Force value locking for DLL off */ +#ifdef NEW_MEMORY_TIMING + ldr r1, =0x6A3B3B01 +#endif + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + +#ifndef NEW_MEMORY_TIMING + /* DLL off */ + ldr r1, =0x50101009 + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET +#endif + + /* auto refresh off */ +#ifdef NEW_MEMORY_TIMING + ldr r1, =0x0FFF1010 + ldr r2, =0x0FFF10B0 +#else + ldr r1, =0xff001010 | (1 << 7) + ldr r2, =0xff001010 | (1 << 7) +#endif + str r1, [r0, #0x000] @ CONCONTROL_OFFSET + strne r2, [r6, #0x000] @ CONCONTROL_OFFSET + + /* + * Burst Length 4, 2 chips, 32-bit, LPDDR + * OFF: dynamic self refresh, force precharge, dynamic power down off + */ +#ifdef NEW_MEMORY_TIMING + ldr r1, =0x00202100 + ldr r2, =0x00212100 +#else + ldr r1, =0x00212100 + ldr r2, =0x00212100 +#endif + str r1, [r0, #0x004] @ MEMCONTROL_OFFSET + strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET + + /* + * Note: + * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only) + * So finally Bank1 OneDRAM should address start at at 0x3000'0000 + */ + + /* + * DMC0: CS0 : S5PC100/S5PC110 + * 0x30 -> 0x30000000 + * 0xf8 -> 0x37FFFFFF + * [15:12] 0: Linear + * [11:8 ] 2: 9 bits + * [ 7:4 ] 2: 14 bits + * [ 3:0 ] 2: 4 banks + */ + ldr r3, =0x30f80222 +swap_memory: + str r3, [r0, #0x008] @ MEMCONFIG0_OFFSET + + /* + * DMC1: CS0 : S5PC110 + * 0x40 -> 0x40000000 + * 0xf8 -> 0x47FFFFFF (1Gib) + * 0x40 -> 0x40000000 + * 0xf0 -> 0x4FFFFFFF (2Gib) + * [15:12] 0: Linear + * [11:8 ] 2: 9 bits - Col (1Gib) + * [11:8 ] 3: 10 bits - Col (2Gib) + * [ 7:4 ] 2: 14 bits - Row + * [ 3:0 ] 2: 4 banks + */ + /* Default : 2GiB */ + ldr r4, =0x40f00322 @ 2Gib + ldr r5, =0x50f80222 + cmp r9, #1 + ldreq r4, =0x40f80222 @ 1Gib + cmp r9, #3 + ldreq r5, =0x50f80222 @ 2Gib + 1Gib + cmp r9, #4 + ldreq r5, =0x50f00322 @ 2Gib + 2Gib + + cmp r7, r8 + strne r4, [r6, #0x008] @ MEMCONFIG0_OFFSET + strne r5, [r6, #0x00C] @ MEMCONFIG1_OFFSET + + /* + * DMC0: CS1: S5PC100 + * 0x38 -> 0x38000000 + * 0xf8 -> 0x3fFFFFFF + * [15:12] 0: Linear + * [11:8 ] 2: 9 bits + * [ 7:4 ] 2: 14 bits + * [ 3:0 ] 2: 4 banks + */ + eoreq r3, r3, #0x08000000 + streq r3, [r0, #0xc] @ MEMCONFIG1_OFFSET + +#ifdef NEW_MEMORY_TIMING + ldr r1, =0xFF000000 +#else + ldr r1, =0x20000000 +#endif + str r1, [r0, #0x014] @ PRECHCONFIG_OFFSET + strne r1, [r0, #0x014] @ PRECHCONFIG_OFFSET + strne r1, [r6, #0x014] @ PRECHCONFIG_OFFSET + + /* + * S5PC100: + * DMC: CS0: 166MHz + * CS1: 166MHz + * S5PC110: + * DMC0: CS0: 166MHz + * DMC1: CS0: 200MHz + * + * 7.8us * 200MHz %LE %LONG1560(0x618) + * 7.8us * 166MHz %LE %LONG1294(0x50E) + * 7.8us * 133MHz %LE %LONG1038(0x40E), + * 7.8us * 100MHz %LE %LONG780(0x30C), + */ + ldr r1, =0x0000050E + str r1, [r0, #0x030] @ TIMINGAREF_OFFSET + ldrne r1, =0x00000618 + strne r1, [r6, #0x030] @ TIMINGAREF_OFFSET + +#ifdef NEW_MEMORY_TIMING + ldr r1, =0x14233287 +#else + ldr r1, =0x0c233287 +#endif + str r1, [r0, #0x034] @ TIMINGROW_OFFSET + ldrne r1, =0x11344309 + strne r1, [r6, #0x034] @ TIMINGROW_OFFSET + +#ifdef NEW_MEMORY_TIMING + ldr r1, =0x12130005 +#else + ldr r1, =0x32330303 +#endif + str r1, [r0, #0x038] @ TIMINGDATA_OFFSET + ldrne r1, =0x12130005 + strne r1, [r6, #0x038] @ TIMINGDATA_OFFSET + + /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */ +#ifdef NEW_MEMORY_TIMING + ldr r1, =0x0E140222 +#else + ldr r1, =0x04141433 +#endif + str r1, [r0, #0x03C] @ TIMINGPOWER_OFFSET + ldrne r1, =0x0E190222 + strne r1, [r6, #0x03C] @ TIMINGPOWER_OFFSET + + /* chip0 Deselect */ + ldr r1, =0x07000000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip0 PALL */ + ldr r1, =0x01000000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip0 REFA */ + ldr r1, =0x05000000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + /* chip0 REFA */ + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */ + ldr r1, =0x00000032 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 Deselect */ + ldr r1, =0x07100000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 PALL */ + ldr r1, =0x01100000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 REFA */ + ldr r1, =0x05100000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + /* chip1 REFA */ + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */ + ldr r1, =0x00100032 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* auto refresh on */ +#ifdef NEW_MEMORY_TIMING + ldr r1, =0x0FFF10B0 +#else + ldr r1, =0xFF002030 | (1 << 7) +#endif + str r1, [r0, #0x000] @ CONCONTROL_OFFSET + strne r1, [r6, #0x000] @ CONCONTROL_OFFSET + + /* PwrdnConfig */ +#ifdef NEW_MEMORY_TIMING + ldr r1, =0xFFFF00FF +#else + ldr r1, =0x00100002 +#endif + str r1, [r0, #0x028] @ PWRDNCONFIG_OFFSET + strne r1, [r6, #0x028] @ PWRDNCONFIG_OFFSET + +#ifdef NEW_MEMORY_TIMING + /* DMC0: 1 chip, DMC1: 2 chips */ + ldr r1, =0x00202113 + ldr r2, =0x00212113 +#else + ldr r1, =0xff212100 +#endif + str r1, [r0, #0x004] @ MEMCONTROL_OFFSET + strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET + + /* Skip when S5PC110 */ + bne 1f + + /* Check OneDRAM access area at s5pc100 */ + ldreq r3, =0x38f80222 + ldreq r1, =0x37ffff00 + str r3, [r1] + ldr r2, [r1] + cmp r2, r3 + beq swap_memory +1: + mov pc, lr + + .ltorg diff --git a/board/samsung/p1p2/modem_boot.c b/board/samsung/p1p2/modem_boot.c new file mode 100644 index 0000000..3ee35c1 --- /dev/null +++ b/board/samsung/p1p2/modem_boot.c @@ -0,0 +1,397 @@ +/* + * need copyright + */ + +#include +#include +#include +#include +#include +#include "psi_ram.h" + +#define OneDRAM_B_BANK_BASEADDR 0x35000000 + +#define MODEM_OS_BASEADDR OneDRAM_B_BANK_BASEADDR +#define MODEM_EEP_STATIC_BASEADDR (MODEM_OS_BASEADDR + 0x870000) +#define MODEM_EEP_CAL_BAK_BASEADDR (MODEM_OS_BASEADDR + 0x880000) +#define MODEM_EEP_DYNAMIC_BASEADDR (MODEM_OS_BASEADDR + 0x890000) +#define MODEM_EEP_SECURITY_BASEADDR (MODEM_OS_BASEADDR + 0x8A0000) + +#define OneDRAMREG_BASEADDR (OneDRAM_B_BANK_BASEADDR + 0xFFF800) + +#define rOneDRAM_SEMAPHORE (*(volatile int*)(OneDRAMREG_BASEADDR)) +#define rOneDRAM_MAILBOX_AB (*(volatile int*)(OneDRAMREG_BASEADDR + 0x20)) +#define rOneDRAM_MAILBOX_BA (*(volatile int*)(OneDRAMREG_BASEADDR + 0x40)) + +/* primitive IPC on OneDRAM */ +#define IPC_CP_READY_FOR_LOADING 0x12341234 +#define IPC_CP_IMG_LOADED 0x45674567 +#define IPC_CP_READY 0x23 +#define IPC_BOOT_DONE 0x89EF89EF + +#define CP_BOOT_MODE_NORMAL 0x0a +#define CP_BOOT_MODE_PTEST 0x0b + +#define CP_HAS_SEM 0x0 +#define AP_HAS_SEM 0x1 + +#define RETRY 3 + +#define IND 0x30 +#define VERS 0xf0 +#define CRC_OK 0x01 +#define CRC_ERR 0xff + +extern struct serial_device s5pc1xx_serial3_device; +static struct s5pc110_gpio *gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE; + +int uart_serial_pollc(struct serial_device *uart, int retry) +{ + int i = 0; + + for (i = 0; i < retry; i++) { + if (uart->tstc()) + return uart->getc(); + udelay(1000); + } + + return -1; +} + +enum { + MACH_UNIVERSAL, + MACH_TICKERTAPE, + MACH_AQUILA, +}; + +DECLARE_GLOBAL_DATA_PTR; + +static int get_machine_id(void) +{ + if (cpu_is_s5pc100()) + return -1; + + return gd->bd->bi_arch_number - 3100; +} + +static int machine_is_aquila(void) +{ + return get_machine_id() == MACH_AQUILA; +} + +static int machine_is_tickertape(void) +{ + return get_machine_id() == MACH_TICKERTAPE; +} + +static int aquila_infineon_modem_on(void) +{ + unsigned int dat, exit = 0; + unsigned int nInfoSize; + unsigned char *pDataPSI; + int nCnt; + int nCoreVer, nSizePSI, nCRC; + int ack; + int i, tmp; + + /* Infineon modem */ + /* 1. Modem gpio init */ + /* Phone_on */ + gpio_direction_output(&gpio->gpio_j1, 0, 1); + gpio_set_pull(&gpio->gpio_j1, 0, GPIO_PULL_NONE); + + /* CP_Reset */ + gpio_direction_output(&gpio->gpio_h3, 7, 1); + gpio_set_pull(&gpio->gpio_h3, 7, GPIO_PULL_NONE); + + /* nINT_ONEDRAN_AP */ + gpio_direction_output(&gpio->gpio_h1, 3, 1); + gpio_set_pull(&gpio->gpio_h1, 3, GPIO_PULL_NONE); + + /* 2. Uart3 init */ + gpio_cfg_pin(&gpio->gpio_a1, 2, 0x2); + gpio_cfg_pin(&gpio->gpio_a1, 3, 0x2); + gpio_set_pull(&gpio->gpio_a1, 2, GPIO_PULL_NONE); + gpio_set_pull(&gpio->gpio_a1, 3, GPIO_PULL_NONE); + + /* reset and enable FIFOs, set triggers to the maximum */ + writel(0x0, 0xE2900C08); + writel(0x0, 0xE2900C0C); + /* 8N1 */ + writel(0x3, 0xE2900C00); + /* No interrupts, no DMA, pure polling */ + writel(0x245, 0xE2900C04); + s5pc1xx_serial3_device.setbrg(); + + /* 3. Modem reset */ + while (1) { + /* PHONE_ON -> low */ + gpio_set_value(&gpio->gpio_j1, 0, 0); + + /* CP_RESET -> low */ + gpio_set_value(&gpio->gpio_h3, 7, 0); + + udelay(200*1000); /* 200ms */ + + /* CP_RESET -> high */ + gpio_set_value(&gpio->gpio_h3, 7, 1); + + /* PHONE_ON -> high */ + gpio_set_value(&gpio->gpio_j1, 0, 1); + + udelay(27*1000); /* > 26.6ms */ + + udelay(40*1000); /* Power stabilization */ + + if (++exit > RETRY) + break; + + printf("********************************\n"); + printf(" Reset and try to send PSI : #%d\n", exit); + + /* Drain Rx Serial */ + tmp = 0; + while (tmp != -1) + tmp = uart_serial_pollc(&s5pc1xx_serial3_device, 5); + + /* Sending "AT" in ASCII */ + for (nCnt = 0; nCnt < 20; nCnt++) { + s5pc1xx_serial3_device.puts("AT"); + nCoreVer = + uart_serial_pollc(&s5pc1xx_serial3_device, 5); + + if (nCoreVer == VERS) + break; + + /* + * Send "AT" at 50ms internals till the bootcore + * version is received + */ + udelay(50*1000); /* 50mec */ + } + + /* if fail to receive Modem core version restart all process */ + if (nCnt == 20) + continue; + + nInfoSize = uart_serial_pollc(&s5pc1xx_serial3_device, 5); + printf("Got Bootcore version and related info!!!\n" + " - nCoreVer = 0x%x \n - nInfoSize = 0x%x\n", + nCoreVer, nInfoSize); + + /* Drain Rx Serial */ + tmp = 0; + while (tmp != -1) + tmp = uart_serial_pollc(&s5pc1xx_serial3_device, 5); + + /* INDICATION BYTE */ + s5pc1xx_serial3_device.putc(IND); + + /* 16 bit length in little endian format */ + nSizePSI = sizeof(g_tblBin); + s5pc1xx_serial3_device.putc(nSizePSI & 0xff); + s5pc1xx_serial3_device.putc(nSizePSI >> 8); + + printf("Sending PSI data!!!\n - Len = %d\n", nSizePSI); + + /* Data bytes of PSI */ + pDataPSI = g_tblBin; + nCRC = 0; + for (nCnt = 0; nCnt < nSizePSI ; nCnt++) { + s5pc1xx_serial3_device.putc(*pDataPSI); + nCRC ^= *pDataPSI++; + } + + /* CRC of PSI */ + s5pc1xx_serial3_device.putc(nCRC); + + udelay(10*1000); /* 10mec */ + + /* Getting ACK */ + ack = uart_serial_pollc(&s5pc1xx_serial3_device, 5); + + if (ack == CRC_OK) { + printf("PSI sending was sucessful\n"); + } else { + printf("PSI sending was NOT sucessful\n" + " - ack(0x%x)\n - nCRC(0x%x)\n", ack, nCRC); + continue; + } + + /* check Modem reaction */ + while (gpio_get_value(&gpio->gpio_h1, 3)) + ; + + if (rOneDRAM_MAILBOX_AB != IPC_CP_READY_FOR_LOADING) { + printf("OneDRAM is NOT initialized for Modem\n"); + printf("Modem downloading is failed!!!\n"); + return 1; + } + + printf("Modem is ready for loading\n"); + + /* + * Do not support full-booting sequence, + * Full support will be done by Kernel + */ + return 0; + + printf("OneDRAM is mailbox(expecting 0x21), " + "rOneDRAM_MAILBOX_AB=%x\n", + rOneDRAM_MAILBOX_AB); + while (rOneDRAM_SEMAPHORE == CP_HAS_SEM) { + printf("OneDRAM semaphore is NOT available"); + udelay(100*1000); + } + + /* load cp image */ + printf("Now, load CP image and static EEP at B-bank of OneDRAM\n"); + printf("By pausing and load .fls[0x51000000] and .eep[0x51870000]\n"); + printf("images to memory through EJTAG\n"); + + for (i = 0; i < 60; i++) { + udelay(100 * 1000); + printf("*"); + } + printf("\n"); + +/* + break; + LoadCPImage(); +*/ + + printf("Thank you for loading\n"); + + rOneDRAM_SEMAPHORE = CP_HAS_SEM; + rOneDRAM_MAILBOX_BA = IPC_CP_IMG_LOADED; + + /* check Modem reaction */ + while (gpio_get_value(&gpio->gpio_h1, 3)) + ; + + if (rOneDRAM_MAILBOX_AB != IPC_CP_READY) { + printf("Modem is NOT ready to boot\n"); + printf("Modem booting is failed!!!\n"); + return 1; + } + + printf("Modem is done copying CP images\n"); + printf("OneDRAM is mailbox message(expecting 0x23), " + "rOneDRAM_MAILBOX_AB=%x\n", + rOneDRAM_MAILBOX_AB); + while (rOneDRAM_SEMAPHORE == CP_HAS_SEM) { + printf("OneDRAM semaphore is NOT available"); + udelay(100*1000); + } + + rOneDRAM_SEMAPHORE = CP_HAS_SEM; + + rOneDRAM_MAILBOX_BA = IPC_BOOT_DONE; + printf("Modem is now running\n"); + + for (i = 0; i < 50; i++) { + udelay(100 * 1000); + if (rOneDRAM_SEMAPHORE == AP_HAS_SEM) + printf("S"); + else + printf("*"); + } + printf("\n"); + + rOneDRAM_MAILBOX_BA = 0x05; /* FIXME */ + + for (i = 0; i < 50; i++) { + udelay(100*1000); + if (rOneDRAM_SEMAPHORE == AP_HAS_SEM) + printf("S"); + else + printf("*"); + } + printf("\n"); + printf("Waiting for 5 secs for modem to respond\n"); + + for (i = 0; i < 50000; i++) { + dat = gpio_get_value(&gpio->gpio_h1, 3); + if (dat == 0) + break; + udelay(100); + } + + if (tmp == 1) + printf("No response from Modem!!!\n"); + + break; + } + + return 0; +} + +static void mdelay(int msec) +{ + int i; + for (i = 0; i < msec; i++) + udelay(1000); +} + +static void tickertape_modem_on(void) +{ + int gpio_phone_on, gpio_cp_rst; + + printf("Tickertape phone on\n"); + + gpio_phone_on = 0; + gpio_cp_rst = 7; + + gpio_direction_output(&gpio->gpio_j1, gpio_phone_on, 0); + gpio_direction_output(&gpio->gpio_h3, gpio_cp_rst, 0); + + gpio_set_value(&gpio->gpio_h3, gpio_cp_rst, 0); + gpio_set_value(&gpio->gpio_j1, gpio_phone_on, 1); + mdelay(100); + gpio_set_value(&gpio->gpio_h3, gpio_cp_rst, 1); + mdelay(900); + gpio_set_value(&gpio->gpio_j1, gpio_phone_on, 0); +} + +int do_modem(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *cmd; + + cmd = argv[1]; + + switch (argc) { + case 0: + case 1: + goto usage; + + case 2: + if (strncmp(cmd, "on", 2) == 0) { + if (machine_is_aquila()) + aquila_infineon_modem_on(); + if (machine_is_tickertape()) + tickertape_modem_on(); + return 0; + } + break; + } + + return 0; +usage: + cmd_usage(cmdtp); + return 1; +} + +void LoadCPImage(void) +{ +#if 0 + /* load CP image */ + LoadPartition(PARTITION_ID_MODEM_OS , (UINT8 *)MODEM_OS_BASEADDR, 0); + /* load CP EEP data */ + LoadValidEEP(); +#endif +} + +U_BOOT_CMD(modem, CONFIG_SYS_MAXARGS, 1, do_modem, + "initialize the Modem", + "on" +); diff --git a/board/samsung/p1p2/onenand.c b/board/samsung/p1p2/onenand.c new file mode 100644 index 0000000..057bc6a --- /dev/null +++ b/board/samsung/p1p2/onenand.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2008-2009 Samsung Electronics + * Kyungmin Park + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include + +void onenand_board_init(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + int value; + + if (cpu_is_s5pc110()) { + this->base = (void *) 0xB0000000; + this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; + } else { + struct s5pc100_clock *clk = + (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct samsung_onenand *onenand; + + this->base = (void *) S5PC100_ONENAND_BASE; + onenand = (struct samsung_onenand *)this->base; + + /* D0 Domain system 1 clock gating */ + value = readl(&clk->gate_d00); + value &= ~(1 << 2); /* CFCON */ + value |= (1 << 2); + writel(value, &clk->gate_d00); + + /* D0 Domain memory clock gating */ + value = readl(&clk->gate_d01); + value &= ~(1 << 2); /* CLK_ONENANDC */ + value |= (1 << 2); + writel(value, &clk->gate_d01); + + /* System Special clock gating */ + value = readl(&clk->gate_sclk0); + value &= ~(1 << 2); /* OneNAND */ + value |= (1 << 2); + writel(value, &clk->gate_sclk0); + + value = readl(&clk->src0); + value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */ + value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */ + writel(value, &clk->src0); + + value = readl(&clk->div1); + value &= ~(3 << 16); + value |= (1 << 16); + writel(value, &clk->div1); + + writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset); + + while (!(readl(&onenand->int_err_stat) & RST_CMP)) + continue; + + writel(RST_CMP, &onenand->int_err_ack); + + /* + * Access_Clock [2:0] + * 166 MHz, 134 Mhz : 3 + * 100 Mhz, 60 Mhz : 2 + */ + writel(0x3, &onenand->acc_clock); + + writel(INT_ERR_ALL, &onenand->int_err_mask); + writel(1 << 0, &onenand->int_pin_en); /* Enable */ + + value = readl(&onenand->int_err_mask); + value &= ~RDY_ACT; + writel(value, &onenand->int_err_mask); + + s3c_onenand_init(mtd); + } +} diff --git a/board/samsung/p1p2/p1p2.c b/board/samsung/p1p2/p1p2.c new file mode 100644 index 0000000..e498b03 --- /dev/null +++ b/board/samsung/p1p2/p1p2.c @@ -0,0 +1,2408 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Kyungmin Park + * Minkyu Kang + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define C100_MACH_START 3000 +#define C110_MACH_START 3100 + +static unsigned int board_rev; +static unsigned int battery_soc; +static struct s5pc110_gpio *s5pc110_gpio; + +enum { + I2C_2, + I2C_GPIO3, + I2C_PMIC, + I2C_GPIO5, + I2C_GPIO6, + I2C_GPIO7, +}; + +/* + * i2c 2 + * SDA: GPD1[4] + * SCL: GPD1[5] + */ +static struct i2c_gpio_bus_data i2c_2 = { + .sda_pin = 4, + .scl_pin = 5, +}; + +/* + * i2c gpio3 + * SDA: GPJ3[6] + * SCL: GPJ3[7] + */ +static struct i2c_gpio_bus_data i2c_gpio3 = { + .sda_pin = 6, + .scl_pin = 7, +}; + +/* + * i2c pmic + * SDA: GPJ4[0] + * SCL: GPJ4[3] + */ +static struct i2c_gpio_bus_data i2c_pmic = { + .sda_pin = 0, + .scl_pin = 3, +}; + +/* + * i2c gpio5 + * SDA: MP05[3] + * SCL: MP05[2] + */ +static struct i2c_gpio_bus_data i2c_gpio5 = { + .sda_pin = 3, + .scl_pin = 2, +}; + +/* + * i2c gpio6 + * SDA: GPJ3[0] + * SCL: GPJ3[1] + */ +static struct i2c_gpio_bus_data i2c_gpio6 = { + .sda_pin = 0, + .scl_pin = 1, +}; + +/* + * i2c gpio6 - cypress + * SDA: GPJ3[4] + * SCL: GPJ3[5] + */ +static struct i2c_gpio_bus_data i2c_cypress_gpio6 = { + .sda_pin = 4, + .scl_pin = 5, +}; + +/* + * i2c gpio7 - cypress + * SDA: MP05[6] + * SCL: MP05[4] + */ +static struct i2c_gpio_bus_data i2c_cypress_gpio7 = { + .sda_pin = 6, + .scl_pin = 4, +}; + +static struct i2c_gpio_bus i2c_gpio[] = { + { + .bus = &i2c_2, + }, { + .bus = &i2c_gpio3, + }, { + .bus = &i2c_pmic, + }, { + .bus = &i2c_gpio5, + }, { + .bus = &i2c_gpio6, + }, { + .bus = NULL, + } +}; + +u32 get_board_rev(void) +{ + return board_rev; +} + +static int hwrevision(int rev) +{ + return (board_rev & 0xf) == rev; +} + +enum { + MACH_UNIVERSAL, + MACH_TICKERTAPE, + MACH_AQUILA, + MACH_P1P2, + MACH_GEMINUS, + MACH_CYPRESS, +}; +#ifdef CONFIG_LCD +typedef enum { + LCD_NONE, + LCD_AMOLED, + LCD_TFT, +} lcd_type_t; + +static lcd_type_t lcd_type; +#endif + +#define SPLIT_SCREEN_FEATURE 0x100 + +/* board is MACH_AQUILA and board is like below. */ +#define J1_B2_BOARD 0x200 +#define LIMO_UNIVERSAL_BOARD 0x400 +#define LIMO_REAL_BOARD 0x800 +#define MEDIA_BOARD 0x1000 +#define BAMBOO_BOARD 0x2000 +/* board is MACH_P1P2 and board is like below. */ +#define P1_REAL_BOARD 0x200 +#define P2_REAL_BOARD 0x400 + +#define BOARD_MASK 0xF00 + +static int c110_machine_id(void) +{ + return gd->bd->bi_arch_number - C110_MACH_START; +} + +static int machine_is_aquila(void) +{ + return c110_machine_id() == MACH_AQUILA; +} + +static int machine_is_p1p2(void) +{ + return c110_machine_id() == MACH_P1P2; +} + +static int machine_is_tickertape(void) +{ + return c110_machine_id() == MACH_TICKERTAPE; +} + +static int machine_is_geminus(void) +{ + return c110_machine_id() == MACH_GEMINUS; +} + +static int machine_is_cypress(void) +{ + return c110_machine_id() == MACH_CYPRESS; +} + +static int board_is_limo_universal(void) +{ + return machine_is_aquila() && (board_rev & LIMO_UNIVERSAL_BOARD); +} + +static int board_is_limo_real(void) +{ + return machine_is_aquila() && (board_rev & LIMO_REAL_BOARD); +} + +static int board_is_media(void) +{ + return machine_is_aquila() && (board_rev & MEDIA_BOARD); +} + +static int board_is_bamboo(void) +{ + return machine_is_aquila() && (board_rev & BAMBOO_BOARD); +} + +static int board_is_j1b2(void) +{ + return machine_is_aquila() && (board_rev & J1_B2_BOARD); +} + +static int board_is_p2_real(void) +{ + return machine_is_p1p2() && (board_rev & P2_REAL_BOARD); +} +#ifdef CONFIG_LCD +static int lcd_is_amoled(void) +{ + return lcd_type == LCD_AMOLED; +} + +static int lcd_is_tft(void) +{ + return lcd_type == LCD_TFT; +} +#endif +static void enable_battery(void); + +void i2c_init_board(void) +{ + struct s5pc110_gpio *gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE; + int num_bus; + + if (cpu_is_s5pc100()) + return; + + num_bus = ARRAY_SIZE(i2c_gpio); + + if (machine_is_cypress()) { + i2c_gpio[I2C_GPIO6].bus = &i2c_cypress_gpio6; + i2c_gpio[I2C_GPIO7].bus = &i2c_cypress_gpio7; + i2c_gpio[I2C_GPIO7].bus->gpio_base = + (unsigned int)&gpio->gpio_mp0_5; + } else { + num_bus--; + } + + i2c_gpio[I2C_2].bus->gpio_base = (unsigned int)&gpio->gpio_d1; + i2c_gpio[I2C_GPIO3].bus->gpio_base = (unsigned int)&gpio->gpio_j3; + i2c_gpio[I2C_PMIC].bus->gpio_base = (unsigned int)&gpio->gpio_j4; + i2c_gpio[I2C_GPIO5].bus->gpio_base = (unsigned int)&gpio->gpio_mp0_5; + i2c_gpio[I2C_GPIO6].bus->gpio_base = (unsigned int)&gpio->gpio_j3; + + i2c_gpio_init(i2c_gpio, num_bus, I2C_PMIC); + + /* Reset on max17040 early */ + if (battery_soc == 0) + enable_battery(); +} + +#ifdef CONFIG_MISC_INIT_R +#define DEV_INFO_LEN 512 +static char device_info[DEV_INFO_LEN]; +static int display_info; + +static void dprintf(const char *fmt, ...) +{ + va_list args; + uint i; + char buf[128]; + + va_start(args, fmt); + i = vsprintf(buf, fmt, args); + va_end(args); + + buf[127] = 0; + + if ((strlen(device_info) + strlen(buf)) > (DEV_INFO_LEN - 1)) { + puts("Flushing device info...\n"); + puts(device_info); + device_info[0] = 0; + } + strcat(device_info, buf); + puts(buf); +} + +#ifdef CONFIG_S5PC1XXFB +static void display_device_info(void) +{ + if (!display_info) + return; + + init_font(); + set_font_xy(0, 450); + set_font_color(FONT_WHITE); + fb_printf(device_info); + exit_font(); + + memset(device_info, 0x0, DEV_INFO_LEN); + + udelay(5 * 1000 * 1000); +} +#endif + +static const char *board_name[] = { + "Universal", + "TickerTape", + "Aquila", + "P1P2", + "Geminus", + "Cypress", +}; + +enum { + MEM_4G1G1G, + MEM_4G2G1G, + MEM_4G3G1G, + MEM_4G4G1G, +}; + +static char feature_buffer[32]; + +static char *display_features(int board, int board_rev) +{ + int count = 0; + char *buf = feature_buffer; + + if (board == MACH_AQUILA) { + if (board_rev & SPLIT_SCREEN_FEATURE) + count += sprintf(buf + count, " - SplitScreen"); + if (board_rev & J1_B2_BOARD) + count += sprintf(buf + count, " - J1 B2 board"); + /* Limo Real or Universal */ + if (board_rev & LIMO_REAL_BOARD) + count += sprintf(buf + count, " - Limo Real"); + else if (board_rev & LIMO_UNIVERSAL_BOARD) + count += sprintf(buf + count, " - Limo Universal"); + if (board_rev & MEDIA_BOARD) + count += sprintf(buf + count, " - Media"); + if (board_rev & BAMBOO_BOARD) + count += sprintf(buf + count, " - Bamboo"); + } else if (board == MACH_P1P2) { + /* P1P2 */ + if (board_rev & P1_REAL_BOARD) + count += sprintf(buf + count, " - P1 Real"); + else if (board_rev & P2_REAL_BOARD) + count += sprintf(buf + count, " - P2 Real"); + else + count += sprintf(buf + count, " - Universal"); + } + + return buf; +} + +static void check_board_revision(int board, int rev) +{ + switch (board) { + case MACH_AQUILA: + /* Limo Real or Universal */ + if (rev & LIMO_UNIVERSAL_BOARD) + board_rev &= ~J1_B2_BOARD; + if (rev & LIMO_REAL_BOARD) { + board_rev &= ~(J1_B2_BOARD | + LIMO_UNIVERSAL_BOARD); + } + if (rev & MEDIA_BOARD) + board_rev &= ~(J1_B2_BOARD | + LIMO_UNIVERSAL_BOARD); + if (rev & BAMBOO_BOARD) + board_rev &= ~(J1_B2_BOARD | + LIMO_UNIVERSAL_BOARD | + LIMO_REAL_BOARD | + MEDIA_BOARD); + break; + case MACH_P1P2: + break; + case MACH_CYPRESS: + /* There's no HWREV_MODE3 */ + board_rev &= ~(1 << 3); + /* Fall through */ + case MACH_TICKERTAPE: + case MACH_GEMINUS: + board_rev &= ~BOARD_MASK; + break; + default: + break; + } +} + +static unsigned int get_hw_revision(struct s5pc1xx_gpio_bank *bank) +{ + unsigned int rev; + + gpio_direction_input(bank, 1); + gpio_direction_input(bank, 2); + gpio_direction_input(bank, 3); + gpio_direction_input(bank, 4); + + gpio_set_pull(bank, 1, GPIO_PULL_NONE); /* HWREV_MODE3 */ + gpio_set_pull(bank, 2, GPIO_PULL_NONE); /* HWREV_MODE0 */ + gpio_set_pull(bank, 3, GPIO_PULL_NONE); /* HWREV_MODE1 */ + gpio_set_pull(bank, 4, GPIO_PULL_NONE); /* HWREV_MODE2 */ + + rev = gpio_get_value(bank, 2); + rev |= (gpio_get_value(bank, 3) << 1); + rev |= (gpio_get_value(bank, 4) << 2); + rev |= (gpio_get_value(bank, 1) << 3); + + return rev; +} + +static void check_hw_revision(void) +{ + unsigned int board = MACH_UNIVERSAL; /* Default is Universal */ + + if (cpu_is_s5pc100()) { + struct s5pc100_gpio *gpio = + (struct s5pc100_gpio *)S5PC100_GPIO_BASE; + + board_rev = get_hw_revision(&gpio->gpio_j0); + + /* C100 TickerTape */ + if (board_rev == 3) + board = MACH_TICKERTAPE; + } else { + struct s5pc110_gpio *gpio = + (struct s5pc110_gpio *)S5PC110_GPIO_BASE; + + board_rev = get_hw_revision(&gpio->gpio_j0); + + /* + * Note Check 'Aquila' board first + * + * TT: TickerTape + * SS: SplitScreen + * LRA: Limo Real Aquila + * LUA: Limo Universal Aquila + * OA: Old Aquila + * P1P2: Smart Book + * CYP: Cypress + * BB: Bamboo + * + * ADDR = 0xE0200000 + OFF + * + * OFF Universal BB LRA LUA OA TT SS P1P2 CYP + * J1: 0x0264 0x10 0x10 0x00 0x00 0x00 0x00 0x00 0x00 + * J2: 0x0284 0x01 0x10 0x00 + * H1: 0x0C24 W 0x28 0xA8 0x1C 0x18 0x0F + * H3: 0x0C64 0x03 0x07 0x0F 0xff + * D1: 0x00C4 0x0F 0x3F 0x3F 0x0F 0xXC 0x3F + * I: 0x0224 0x02 0x00 0x08 + * MP03: 0x0324 0x9x 0xbx 0x9x + * MP05: 0x0364 0x80 0x88 + */ + + /* C110 Aquila */ + if (gpio_get_value(&gpio->gpio_j1, 4) == 0) { + board = MACH_AQUILA; + board_rev |= J1_B2_BOARD; + + gpio_set_pull(&gpio->gpio_j2, 6, GPIO_PULL_NONE); + gpio_direction_input(&gpio->gpio_j2, 6); + + /* Check board */ + if (gpio_get_value(&gpio->gpio_h1, 2) == 0) + board_rev |= LIMO_UNIVERSAL_BOARD; + + if (gpio_get_value(&gpio->gpio_h3, 2) == 0) + board_rev |= LIMO_REAL_BOARD; + + if (gpio_get_value(&gpio->gpio_j2, 6) == 1) + board_rev |= MEDIA_BOARD; + + /* set gpio to default value. */ + gpio_set_pull(&gpio->gpio_j2, 6, GPIO_PULL_DOWN); + gpio_direction_output(&gpio->gpio_j2, 6, 0); + } + /* Workaround: C110 Aquila Rev0.6 */ + if (board_rev == 6) { + board = MACH_AQUILA; + board_rev |= LIMO_REAL_BOARD; + } + /* C110 Aquila Bamboo */ + if (gpio_get_value(&gpio->gpio_j2, 0) == 1) { + board = MACH_AQUILA; + board_rev |= BAMBOO_BOARD; + } + + /* C110 TickerTape */ + if (gpio_get_value(&gpio->gpio_d1, 0) == 0 && + gpio_get_value(&gpio->gpio_d1, 1) == 0) + board = MACH_TICKERTAPE; + + /* C110 Cypress: Do first this than P1P2 */ + gpio_set_pull(&gpio->gpio_j2, 2, GPIO_PULL_NONE); + gpio_direction_input(&gpio->gpio_j2, 2); + if (gpio_get_value(&gpio->gpio_j2, 2) == 1) + board = MACH_CYPRESS; + gpio_set_pull(&gpio->gpio_j2, 2, GPIO_PULL_DOWN); + + /* C110 P1P2 */ + if (gpio_get_value(&gpio->gpio_h3, 7) == 1) { + board = MACH_P1P2; + board_rev &= ~BOARD_MASK; + } + + /* set gpio configuration for P1P2. */ + gpio_direction_input(&gpio->gpio_j0, 6); + gpio_direction_input(&gpio->gpio_j0, 7); + + /* + * do not change order below + * because it needs delay to get gpio value. + */ + /* HWREV_MODE4 */ + gpio_set_pull(&gpio->gpio_j0, 7, GPIO_PULL_NONE); + /* HWREV_MODE5 */ + gpio_set_pull(&gpio->gpio_j0, 6, GPIO_PULL_NONE); + + if (gpio_get_value(&gpio->gpio_j0, 7) == 1) { + board = MACH_P1P2; + board_rev &= ~BOARD_MASK; + if (gpio_get_value(&gpio->gpio_j0, 6) == 1) { + board_rev |= P1_REAL_BOARD; + #ifdef CONFIG_LCD + lcd_type = LCD_TFT; + #endif + } + if (gpio_get_value(&gpio->gpio_j0, 6) == 0) + board_rev |= P2_REAL_BOARD; + } + #ifdef CONFIG_LCD + else { + if (gpio_get_value(&gpio->gpio_j0, 6) == 1) { + lcd_type = LCD_AMOLED; + } + } + #endif + + /* set gpio to default value. */ + /* HWREV_MODE4 */ + gpio_set_pull(&gpio->gpio_j0, 6, GPIO_PULL_DOWN); + /* HWREV_MODE5 */ + gpio_set_pull(&gpio->gpio_j0, 7, GPIO_PULL_DOWN); + + if(board != MACH_P1P2) + { + /* C110 Geminus for rev0.0 */ + gpio_set_pull(&gpio->gpio_j1, 2, GPIO_PULL_NONE); + gpio_direction_input(&gpio->gpio_j1, 2); + if (gpio_get_value(&gpio->gpio_j1, 2) == 1) { + board = MACH_GEMINUS; + if ((board_rev & ~BOARD_MASK) == 3) + board_rev &= ~0xff; + } + gpio_set_pull(&gpio->gpio_j1, 2, GPIO_PULL_DOWN); + gpio_direction_output(&gpio->gpio_j1, 2, 0); + + /* C110 Geminus for rev0.1 ~ */ + gpio_set_pull(&gpio->gpio_j0, 6, GPIO_PULL_NONE); + gpio_direction_input(&gpio->gpio_j0, 6); + if (gpio_get_value(&gpio->gpio_j0, 6) == 1) + board = MACH_GEMINUS; + gpio_set_pull(&gpio->gpio_j0, 6, GPIO_PULL_DOWN); + #ifdef CONFIG_LCD + lcd_type = LCD_NONE; /* TODO: if the board is not p1p2, this code should be modified */ + #endif + } + } + + /* Set machine id */ + if (cpu_is_s5pc110()) + gd->bd->bi_arch_number = C110_MACH_START + board; + else + gd->bd->bi_arch_number = C100_MACH_START + board; + + /* Architecture Common settings */ + if (cpu_is_s5pc110()) { + setenv("mtdparts", MTDPARTS_DEFAULT_4KB); + } else { + setenv("bootk", "onenand read 0x30007FC0 0x60000 0x300000; " + "bootm 0x30007FC0"); + setenv("updatek", "onenand erase 0x60000 0x300000; " + "onenand write 0x31008000 0x60000 0x300000"); + } +} + +static void show_hw_revision(void) +{ + int board; + + /* + * Workaround for Rev 0.3 + CP Ver ES 3.1 + * it's Rev 0.4 + */ + if (board_is_limo_real()) { + if (hwrevision(0)) { + /* default is Rev 0.4 */ + board_rev &= ~0xf; + board_rev |= 0x4; + } + } + + if (cpu_is_s5pc110()) + board = gd->bd->bi_arch_number - C110_MACH_START; + else + board = gd->bd->bi_arch_number - C100_MACH_START; + + check_board_revision(board, board_rev); + + /* Set CPU Revision */ + if (board_is_limo_real()) { + if ((board_rev & 0xf) < 8) + s5pc1xx_set_cpu_rev(0); + } else { + s5pc1xx_set_cpu_rev(0); + } + + dprintf("HW Revision:\t%x (%s%s)\n", board_rev, board_name[board], + display_features(board, board_rev)); +} + +static void check_auto_burn(void) +{ + unsigned long magic_base = CONFIG_SYS_SDRAM_BASE + 0x02000000; + unsigned int count = 0; + char buf[64]; + + if (readl(magic_base) == 0x426f6f74) { /* ASICC: Boot */ + printf("Auto burning bootloader\n"); + count += sprintf(buf + count, "run updateb; "); + } + if (readl(magic_base + 0x04) == 0x4b65726e) { /* ASICC: Kern */ + printf("Auto burning kernel\n"); + count += sprintf(buf + count, "run updatek; "); + } + + if (count) { + count += sprintf(buf + count, "reset"); + setenv("bootcmd", buf); + } + + /* Clear the magic value */ + writel(0xa5a55a5a, magic_base); + writel(0xa5a55a5a, magic_base + 0x4); +} + +static void pmic_pin_init(void) +{ + unsigned int reg, value; + + if (cpu_is_s5pc100()) + return; + + /* AP_PS_HOLD: XEINT_0: GPH0[0] + * Note: Don't use GPIO PS_HOLD it doesn't work + */ + reg = S5PC110_PS_HOLD_CONTROL; + value = readl(reg); + value |= S5PC110_PS_HOLD_DIR_OUTPUT | + S5PC110_PS_HOLD_DATA_HIGH | + S5PC110_PS_HOLD_OUT_EN; + writel(value, reg); + + /* nPOWER: XEINT_22: GPH2[6] interrupt mode */ + gpio_cfg_pin(&s5pc110_gpio->gpio_h2, 6, GPIO_IRQ); + gpio_set_pull(&s5pc110_gpio->gpio_h2, 6, GPIO_PULL_UP); +} + +static void enable_ldos(void) +{ + if (cpu_is_s5pc100()) + return; + + if (machine_is_p1p2()) + return; + + /* TOUCH_EN: XMMC3DATA_3: GPG3[6] output high */ + gpio_direction_output(&s5pc110_gpio->gpio_g3, 6, 1); +} + +static void enable_t_flash(void) +{ + if (!(board_is_limo_universal() || board_is_limo_real())) + return; + + /* T_FLASH_EN : XM0ADDR_13: MP0_5[4] output high */ + gpio_direction_output(&s5pc110_gpio->gpio_mp0_5, 4, 1); +} + +static void setup_limo_real_gpios(void) +{ + if (!board_is_limo_real()) + return; + + /* + * Note: Please write GPIO alphabet order + */ + /* CODEC_LDO_EN: XVVSYNC_LDI: GPF3[4] output high */ + gpio_direction_output(&s5pc110_gpio->gpio_f3, 4, 1); + + if (hwrevision(0)) + /* RESET_REQ_N: XM0BEN_1: MP0_2[1] output high */ + gpio_direction_output(&s5pc110_gpio->gpio_mp0_2, 1, 1); + else + /* RESET_REQ_N: XM0CSn_2: MP0_1[2] output high */ + gpio_direction_output(&s5pc110_gpio->gpio_mp0_1, 2, 1); + + /* T_FLASH_DETECT: EINT28: GPH3[4] interrupt mode */ + gpio_cfg_pin(&s5pc110_gpio->gpio_h3, 4, GPIO_IRQ); + gpio_set_pull(&s5pc110_gpio->gpio_h3, 4, GPIO_PULL_UP); +} + +static void setup_media_gpios(void) +{ + if (!board_is_media()) + return; + + /* + * Note: Please write GPIO alphabet order + */ + /* RESET_REQ_N: XM0CSn_2: MP0_1[2] output high */ + gpio_direction_output(&s5pc110_gpio->gpio_mp0_1, 2, 1); + + /* T_FLASH_DETECT: EINT28: GPH3[4] interrupt mode */ + gpio_cfg_pin(&s5pc110_gpio->gpio_h3, 4, GPIO_IRQ); + gpio_set_pull(&s5pc110_gpio->gpio_h3, 4, GPIO_PULL_UP); +} + +static void setup_p1p2_gpios(void) +{ + if (!machine_is_p1p2()) + return; + + /* + * Note: Please write GPIO alphabet order + */ + /* RESET_REQ_N: XM0FRnB[1]: MP0_3[5] output high */ + gpio_direction_output(&s5pc110_gpio->gpio_mp0_3, 5, 1); + /* CODEC_LDO_EN: XM0FRnB[2]: MP0_3[6] output high */ + gpio_direction_output(&s5pc110_gpio->gpio_mp0_3, 6, 1); +} + +#define KBR3 (1 << 3) +#define KBR2 (1 << 2) +#define KBR1 (1 << 1) +#define KBR0 (1 << 0) + +static void check_p2_keypad(void) +{ + unsigned int auto_download = 0; + unsigned char addr = 0x34, val[2]; /* adp5587 key controller */ + int i, ret; + i2c_set_bus_num(I2C_2); + + if (i2c_probe(addr)) { + printf("Can't found adp5587 key controller\n"); + return; + } + /* Row 8, Column 10 */ + val[0] = 0xf; + ret = i2c_write(addr, 0x1D, 1, val, 1); /* Set KP_GPIO1 */ + val[0] = 0xf; + ret |= i2c_write(addr, 0x1E, 1, val, 1); /* Set KP_GPIO2 */ + val[0] = 0x3; + ret |= i2c_write(addr, 0x1F, 1, val, 1); /* Set KP_GPIO3 */ + val[0] = 0x3f; /* CMP2_INT | CMP1_INT | OVR_FLOW_INT | + K_LCK_INT | GPI_INT | KE_INT */ + ret |= i2c_write(addr, 0x02, 1, val, 1); /* Status is W1C */ + val[0] = 0x19; /* INT_CFG | OVR_FLOW_IEN | KE_IEN */ + ret |= i2c_write(addr, 0x01, 1, val, 1); + for (i = 0; i < 10; i++) { + udelay(1000); /* FIXME */ + i2c_read(addr, 0x04 + i, 1, val, 1); + if (val[0] == 0x94) + auto_download = 1; + } + + if (auto_download == 1) + setenv("bootcmd", "usbdown"); +} + +static void check_keypad(void) +{ + unsigned int reg, value; + unsigned int col_mask, row_mask; + unsigned int auto_download = 0; + unsigned int col_value[4], i; + + if (cpu_is_s5pc100()) { + struct s5pc100_gpio *gpio = + (struct s5pc100_gpio *)S5PC100_GPIO_BASE; + + /* Set GPH2[2:0] to KP_COL[2:0] */ + gpio_cfg_pin(&gpio->gpio_h2, 0, 0x3); + gpio_cfg_pin(&gpio->gpio_h2, 1, 0x3); + gpio_cfg_pin(&gpio->gpio_h2, 2, 0x3); + + /* Set GPH3[2:0] to KP_ROW[2:0] */ + gpio_cfg_pin(&gpio->gpio_h3, 0, 0x3); + gpio_cfg_pin(&gpio->gpio_h3, 1, 0x3); + gpio_cfg_pin(&gpio->gpio_h3, 2, 0x3); + + reg = S5PC100_KEYPAD_BASE; + } else { + if (board_is_limo_real() || board_is_limo_universal()) { + row_mask = 0x00FF; + col_mask = 0x0FFF; + } else { + row_mask = 0xFFFF; + col_mask = 0xFFFF; + } + + for (i = 0; i < 4; i++) { + /* Set GPH3[3:0] to KP_ROW[3:0] */ + if (row_mask & (0xF << (i << 2))) { + gpio_cfg_pin(&s5pc110_gpio->gpio_h3, i, 0x3); + if (!machine_is_p1p2()) + gpio_set_pull(&s5pc110_gpio->gpio_h3, + i, GPIO_PULL_UP); + } + + /* Set GPH2[3:0] to KP_COL[3:0] */ + if (col_mask & (0xF << (i << 2))) + gpio_cfg_pin(&s5pc110_gpio->gpio_h2, i, 0x3); + if (machine_is_p1p2()) + gpio_set_pull(&s5pc110_gpio->gpio_h2, i, GPIO_PULL_UP); + } + + reg = S5PC110_KEYPAD_BASE; + } + /* init col */ + value = 0x00; + writel(value, reg + S5PC1XX_KEYIFCOL_OFFSET); + value = readl(reg + S5PC1XX_KEYIFROW_OFFSET); + /* VOLUMEDOWN and CAM(Half shot) Button */ + if ((value & KBR1) == 0) { + i = 0; + while (i < 4) { + value = readl(reg + S5PC1XX_KEYIFCOL_OFFSET); + value |= 0xff; + value &= ~(1 << i); + writel(value, reg + S5PC1XX_KEYIFCOL_OFFSET); + udelay(10*1000); + col_value[i++] = readl(reg + S5PC1XX_KEYIFROW_OFFSET); + } + writel(0x00, reg + S5PC1XX_KEYIFCOL_OFFSET); + + /* expected value is row_value[0] = 0x00 row_value[1] = 0x01 */ + /* workaround */ + if ((col_value[0] & 0x3) == 0x3 && (col_value[1] & 0x3) == 0x3) + auto_download = 1; + + if ((col_value[0] & 0x3) == 0x3 && (col_value[1] & 0x3) != 0x3) + display_info = 1; + if (machine_is_p1p2()) { + if ((col_value[0] & 0xd) == 0xd) + auto_download = 1; + } + } + + if (auto_download) + setenv("bootcmd", "usbdown"); +} + +static void enable_battery(void) +{ + unsigned char val[2]; + unsigned char addr = 0x36; /* max17040 fuel gauge */ + + if (machine_is_aquila()) { + if (board_is_j1b2()) + return; + } + + if (machine_is_tickertape()) + return; + + if (machine_is_cypress()) + i2c_set_bus_num(I2C_GPIO7); + else + i2c_set_bus_num(I2C_GPIO3); + + if(machine_is_p1p2()) + { + return; + } + + if (i2c_probe(addr)) { + printf("Can't found max17040 fuel gauge\n"); + return; + } + + val[0] = 0x54; + val[1] = 0x00; + i2c_write(addr, 0xfe, 1, val, 2); +} + +static void check_battery(void) +{ + unsigned char val[2]; + unsigned char addr = 0x36; /* max17040 fuel gauge */ + + if(machine_is_p1p2()) + { + return; + } + + if (machine_is_aquila()) { + if (board_is_j1b2()) + return; + } + + if (machine_is_tickertape()) + return; + + if (machine_is_cypress()) + i2c_set_bus_num(I2C_GPIO7); + else + i2c_set_bus_num(I2C_GPIO3); + + if (i2c_probe(addr)) { + printf("Can't found max17040 fuel gauge\n"); + return; + } + + i2c_read(addr, 0x04, 1, val, 1); + + dprintf("battery:\t%d%%\n", val[0]); + + battery_soc = val[0]; +} + +static void check_mhl(void) +{ + unsigned char val[2]; + unsigned char addr = 0x39; /* SIL9230 */ + + /* MHL Power enable */ + /* HDMI_EN : GPJ2[2] XMSMDATA_2 output mode */ + gpio_direction_output(&s5pc110_gpio->gpio_j2, 2, 1); + + /* MHL_RST : MP0_4[7] XM0ADDR_7 output mode */ + gpio_direction_output(&s5pc110_gpio->gpio_mp0_4, 7, 0); + + /* 10ms required after reset */ + udelay(10000); + + /* output enable */ + gpio_set_value(&s5pc110_gpio->gpio_mp0_4, 7, 1); + + i2c_set_bus_num(I2C_GPIO5); + + /* set usb path */ + if (i2c_probe(addr)) { + printf("Can't found MHL Chip\n"); + return; + } + + /* + * System Control #1 + * set to Normal operation + */ + val[0] = 0x35; + i2c_write((0x72 >> 1), 0x08, 1, val, 1); + i2c_read((0x72 >> 1), 0x08, 1, val, 1); + + /* + * MHL TX Control #1 + * TERM_MODE [7:6] + * 00 = MHL termination ON + * 11 = MHL termination OFF + */ + val[0] = 0xd0; + i2c_write((0x72 >> 1), 0xa0, 1, val, 1); + i2c_read((0x72 >> 1), 0xa0, 1, val, 1); +} + +static void into_charge_mode(void) +{ + unsigned char addr = 0xCC >> 1; /* max8998 */; + unsigned char val[2]; + unsigned int level; + int i, j; + + i2c_set_bus_num(I2C_PMIC); + + if (i2c_probe(addr)) { + printf("Can't found max8998\n"); + return; + } + + printf("Charge Mode\n"); + + i2c_read(addr, 0x0C, 1, val, 1); + val[0] &= ~(0x7 << 0); + val[0] |= 5; /* 600mA */ + i2c_write(addr, 0x0C, 1, val, 1); + +#ifdef CONFIG_S5PC1XXFB + /* TODO: change to Image animation */ + init_font(); + set_font_xy(0, 0); + set_font_color(FONT_WHITE); + fb_printf("charging"); + + level = battery_soc / 25; + + for (i = 0; i < 3; i++) { + if (level == 0) + udelay(1 * 1000 * 1000); + + for (j = 0; j < 4; j++) { + fb_printf(".."); + + if (j >= level) + udelay(1 * 1000 * 1000); + } + + if (level <= 4) + udelay(1 * 1000 * 1000); + + set_font_xy(0, 0); + set_font_color(FONT_XOR); + fb_printf("charging........"); + + set_font_xy(0, 0); + set_font_color(FONT_WHITE); + fb_printf("charging"); + } + + exit_font(); +#endif + + /* EVT0: sleep 1, EVT1: sleep */ + if (s5pc1xx_get_cpu_rev() == 0) { + run_command("sleep 1", 0); + return; + } + + run_command("sleep", 0); +} + +static void check_micro_usb(int intr) +{ + unsigned char addr; + unsigned char val[2]; + + if (cpu_is_s5pc100()) + return; + + if (board_is_limo_real()) { + if (hwrevision(0) || hwrevision(1)) + return; + } + + if (machine_is_cypress()) + i2c_set_bus_num(I2C_GPIO6); + else + i2c_set_bus_num(I2C_PMIC); + + addr = 0x25; /* fsa9480 */ + if (i2c_probe(addr)) { + printf("Can't found fsa9480\n"); + return; + } + + /* Clear Interrupt */ + if (intr) { + i2c_read(addr, 0x03, 1, val, 2); + udelay(500 * 1000); + } + + /* Read Device Type 1 */ + i2c_read(addr, 0x0a, 1, val, 1); + +#define FSA_DEDICATED_CHARGER (1 << 6) +#define FSA_UART (1 << 3) +#define FSA_USB (1 << 2) + + /* + * If USB, use default 475mA + * If Charger, use 600mA and go to charge mode + */ + if (val[0] & FSA_DEDICATED_CHARGER) + into_charge_mode(); + + /* If Factory Mode is Boot ON-USB, go to download mode */ + i2c_read(addr, 0x07, 1, val, 1); + +#define FSA_ADC_FAC_USB 0x19 +#define FSA_ADC_FAC_UART 0x1d + + if (val[0] == FSA_ADC_FAC_USB) + setenv("bootcmd", "usbdown"); +} + +#define MAX8998_REG_ONOFF1 0x11 +#define MAX8998_REG_ONOFF2 0x12 +#define MAX8998_REG_ONOFF3 0x13 +#define MAX8998_LDO3 (1 << 2) +#define MAX8998_LDO10 (1 << 3) +#define MAX8998_LDO11 (1 << 2) +#define MAX8998_LDO12 (1 << 1) +#define MAX8998_LDO13 (1 << 0) +#define MAX8998_LDO14 (1 << 7) +#define MAX8998_LDO15 (1 << 6) +#define MAX8998_LDO16 (1 << 5) +#define MAX8998_LDO17 (1 << 4) + +static void init_pmic(void) +{ + unsigned char addr; + unsigned char val[2]; + + if (cpu_is_s5pc100()) + return; + + i2c_set_bus_num(I2C_PMIC); + + addr = 0xCC >> 1; /* max8998 */ + if (i2c_probe(addr)) { + printf("Can't found max8998\n"); + return; + } + + /* ONOFF1 */ + i2c_read(addr, MAX8998_REG_ONOFF1, 1, val, 1); + val[0] &= ~MAX8998_LDO3; + i2c_write(addr, MAX8998_REG_ONOFF1, 1, val, 1); + + /* ONOFF2 */ + i2c_read(addr, MAX8998_REG_ONOFF2, 1, val, 1); + /* + * Disable LDO10(VPLL_1.1V), LDO11(CAM_IO_2.8V), + * LDO12(CAM_ISP_1.2V), LDO13(CAM_A_2.8V) + */ + val[0] &= ~(MAX8998_LDO10 | MAX8998_LDO11 | + MAX8998_LDO12 | MAX8998_LDO13); + val[0] |= (1 << 7); + i2c_write(addr, MAX8998_REG_ONOFF2, 1, val, 1); + i2c_read(addr, MAX8998_REG_ONOFF2, 1, val, 1); + /* ONOFF3 */ + i2c_read(addr, MAX8998_REG_ONOFF3, 1, val, 1); + /* + * Disable LDO14(CAM_CIF_1.8), LDO15(CAM_AF_3.3V), + * LDO16(VMIPI_1.8V), LDO17(CAM_8M_1.8V) + */ + val[0] &= ~(MAX8998_LDO14 | MAX8998_LDO15 | + MAX8998_LDO16 | MAX8998_LDO17); + i2c_write(addr, MAX8998_REG_ONOFF3, 1, val, 1); + i2c_read(addr, MAX8998_REG_ONOFF3, 1, val, 1); +} + +#define PDN_MASK(x) (0x3 << ((x) << 1)) + +#define CON_INPUT(x) (0x0 << ((x) << 2)) +#define CON_OUTPUT(x) (0x1 << ((x) << 2)) +#define CON_IRQ(x) (0xf << ((x) << 2)) + +#define DAT_SET(x) (0x1 << (x)) +#define DAT_CLEAR(x) (0x0 << (x)) + +#define OUTPUT0(x) (0x0 << ((x) << 1)) +#define OUTPUT1(x) (0x1 << ((x) << 1)) +#define INPUT(x) (0x2 << ((x) << 1)) + +#define PULL_DIS(x) (0x0 << ((x) << 1)) +#define PULL_DOWN(x) (0x1 << ((x) << 1)) +#define PULL_UP(x) (0x2 << ((x) << 1)) + +#define PREVIOUS(x) (0x3 << ((x) << 1)) + +struct gpio_powermode { + unsigned int conpdn; + unsigned int pudpdn; +}; + +struct gpio_external { + unsigned int con; + unsigned int dat; + unsigned int pud; +}; + +static struct gpio_powermode powerdown_modes[] = { + { /* S5PC110_GPIO_A0_OFFSET */ + INPUT(0) | OUTPUT0(1) | INPUT(2) | OUTPUT0(3) | + INPUT(4) | OUTPUT0(5) | INPUT(6) | OUTPUT0(7), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_GPIO_A1_OFFSET */ + INPUT(0) | OUTPUT0(1) | INPUT(2) | INPUT(3), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3), + }, { /* S5PC110_GPIO_B_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3) | + INPUT(4) | OUTPUT0(5) | OUTPUT0(6) | OUTPUT0(7), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_GPIO_C0_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | INPUT(3) | + OUTPUT0(4), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4), + }, { /* S5PC110_GPIO_C1_OFFSET */ + /* OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3) | + OUTPUT0(4), */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | INPUT(3) | + OUTPUT0(4), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4), + }, { /* S5PC110_GPIO_D0_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3), + }, { /* S5PC110_GPIO_D1_OFFSET */ + INPUT(0) | INPUT(1) | INPUT(2) | INPUT(3) | + INPUT(4) | INPUT(5), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5), + }, { /* S5PC110_GPIO_E0_OFFSET */ + INPUT(0) | INPUT(1) | INPUT(2) | INPUT(3) | + INPUT(4) | INPUT(5) | INPUT(6) | INPUT(7), + PULL_DOWN(0) | PULL_DOWN(1) | PULL_DOWN(2) | PULL_DOWN(3) | + PULL_DOWN(4) | PULL_DOWN(5) | PULL_DOWN(6) | PULL_DOWN(7), + }, { /* S5PC110_GPIO_E1_OFFSET */ + INPUT(0) | INPUT(1) | INPUT(2) | OUTPUT0(3) | + OUTPUT0(4), + PULL_DOWN(0) | PULL_DOWN(1) | PULL_DOWN(2) | PULL_DIS(3) | + PULL_DIS(4), + }, { /* S5PC110_GPIO_F0_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3) | + OUTPUT0(4) | OUTPUT0(5) | OUTPUT0(6) | OUTPUT0(7), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_GPIO_F1_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3) | + OUTPUT0(4) | OUTPUT0(5) | OUTPUT0(6) | OUTPUT0(7), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_GPIO_F2_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3) | + OUTPUT0(4) | OUTPUT0(5) | OUTPUT0(6) | OUTPUT0(7), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_GPIO_F3_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3) | + OUTPUT0(4) | OUTPUT0(5), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5), + }, { /* S5PC110_GPIO_G0_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3) | + OUTPUT0(4) | OUTPUT0(5) | OUTPUT0(6), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6), + }, { /* S5PC110_GPIO_G1_OFFSET */ + OUTPUT0(0) | INPUT(1) | OUTPUT0(2) | INPUT(3) | + INPUT(4) | INPUT(5) | INPUT(6), + PULL_DIS(0) | PULL_UP(1) | PULL_DIS(2) | PULL_UP(3) | + PULL_UP(4) | PULL_UP(5) | PULL_UP(6), + }, { /* S5PC110_GPIO_G2_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3) | + OUTPUT0(4) | OUTPUT0(5) | OUTPUT0(6), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6), + }, { /* S5PC110_GPIO_G3_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT1(2) | INPUT(3) | + OUTPUT0(4) | OUTPUT0(5) | OUTPUT0(6), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6), + }, { /* S5PC110_GPIO_I_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | INPUT(3) | + OUTPUT0(4) | OUTPUT0(5) | OUTPUT0(6), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6), + }, { /* S5PC110_GPIO_J0_OFFSET */ + INPUT(0) | OUTPUT0(1) | INPUT(2) | INPUT(3) | + INPUT(4) | INPUT(5) | OUTPUT0(6) | OUTPUT0(7), + PULL_DOWN(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_GPIO_J1_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3) | + OUTPUT0(4) | OUTPUT0(5) | OUTPUT0(6) | OUTPUT0(7), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_GPIO_J2_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3) | + INPUT(4) | OUTPUT0(5) | INPUT(6) | INPUT(7), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DOWN(6) | PULL_DOWN(7), + }, { /* S5PC110_GPIO_J3_OFFSET */ + INPUT(0) | INPUT(1) | OUTPUT0(2) | OUTPUT0(3) | + OUTPUT1(4) | OUTPUT0(5) | INPUT(6) | INPUT(7), + PULL_DOWN(0) | PULL_DOWN(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_GPIO_J4_OFFSET */ + INPUT(0) | OUTPUT0(1) | OUTPUT0(2) | INPUT(3) | + OUTPUT0(4), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4), + }, { /* S5PC110_MP0_1_OFFSET */ + /* XM0CSN[4]: MP0_1[4] -> output high */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT1(2) | OUTPUT0(3) | + OUTPUT1(4) | OUTPUT0(5) | OUTPUT1(6) | OUTPUT1(7), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_MP0_2_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | INPUT(2) | OUTPUT0(3), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3), + }, { /* S5PC110_MP0_3_OFFSET */ + /* XM0FWEN: MP0_3[2] -> output high */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT1(2) | OUTPUT0(3) | + INPUT(4) | OUTPUT0(5) | OUTPUT0(6) | OUTPUT0(7), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_MP0_4_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | INPUT(3) | + INPUT(4) | OUTPUT0(5) | OUTPUT0(6) | OUTPUT0(7), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DOWN(3) | + PULL_DOWN(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_MP0_5_OFFSET */ + INPUT(0) | OUTPUT0(1) | INPUT(2) | INPUT(3) | + OUTPUT0(4) | OUTPUT0(5) | OUTPUT0(6) | OUTPUT0(7), + PULL_DOWN(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_MP0_6_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3) | + OUTPUT0(4) | OUTPUT0(5) | OUTPUT0(6) | OUTPUT0(7), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, { /* S5PC110_MP0_7_OFFSET */ + OUTPUT0(0) | OUTPUT0(1) | OUTPUT0(2) | OUTPUT0(3) | + OUTPUT0(4) | OUTPUT0(5) | OUTPUT0(6) | OUTPUT0(7), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5) | PULL_DIS(6) | PULL_DIS(7), + }, +}; + +static struct gpio_external external_powerdown_modes[] = { + { /* S5PC110_GPIO_H0_OFFSET */ + CON_OUTPUT(0) | CON_INPUT(1) | CON_OUTPUT(2) | CON_OUTPUT(3) | + CON_OUTPUT(4) | CON_OUTPUT(5) | CON_INPUT(6) | CON_INPUT(7), + DAT_SET(0) | DAT_CLEAR(2) | DAT_CLEAR(3) | + DAT_CLEAR(4) | DAT_CLEAR(5), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DIS(4) | PULL_DIS(5), + }, { /* S5PC110_GPIO_H1_OFFSET */ + /* CON_INPUT(0) | CON_INPUT(1) | CON_OUTPUT(2) | CON_IRQ(3) | + CON_IRQ(4) | CON_INPUT(5) | CON_INPUT(6) | CON_INPUT(7), + DAT_CLEAR(2), + PULL_DOWN(0) | PULL_DOWN(1) | + PULL_DOWN(6), */ + CON_INPUT(0) | CON_INPUT(1) | CON_OUTPUT(2) | CON_IRQ(3) | + CON_INPUT(4) | CON_INPUT(5) | CON_OUTPUT(6) | CON_INPUT(7), + DAT_SET(0), + PULL_DIS(0) | PULL_DIS(1) | PULL_DIS(2) | PULL_DIS(3) | + PULL_DOWN(4), + }, { /* S5PC110_GPIO_H2_OFFSET */ + CON_OUTPUT(0) | CON_OUTPUT(1) | CON_OUTPUT(2) | CON_OUTPUT(3) | + CON_IRQ(4) | CON_IRQ(5) | CON_IRQ(6) | CON_IRQ(7), + DAT_CLEAR(0) | DAT_CLEAR(1) | DAT_CLEAR(2) | DAT_CLEAR(3), + 0, + }, { /* S5PC110_GPIO_H3_OFFSET */ + CON_IRQ(0) | CON_IRQ(1) | CON_IRQ(2) | CON_OUTPUT(3) | + CON_IRQ(4) | CON_INPUT(5) | CON_IRQ(6) | CON_OUTPUT(7), + DAT_CLEAR(3) | DAT_CLEAR(7), + 0, + }, +}; + +static void setup_power_down_mode_registers(void) +{ + struct s5pc110_gpio *gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE; + struct s5pc1xx_gpio_bank *bank; + struct gpio_powermode *p; + struct gpio_external *ge; + int i; + + if (cpu_is_s5pc100()) + return; + + if (!(machine_is_aquila() && board_is_limo_real())) + return; + + bank = &gpio->gpio_a0; + p = powerdown_modes; + + for (i = 0; i < ARRAY_SIZE(powerdown_modes); i++, p++, bank++) { + writel(p->conpdn, &bank->pdn_con); + writel(p->pudpdn, &bank->pdn_pull); + } + /* M299 */ + writel(0xff0022b0, (unsigned int *)0xF0000000); + writel(0xff0022b0, (unsigned int *)0xF1400000); + + + bank = &gpio->gpio_h0; + ge = external_powerdown_modes; + + for (i = 0; i < ARRAY_SIZE(external_powerdown_modes); i++) { + writel(ge->con, &bank->con); + writel(ge->dat, &bank->dat); + writel(ge->pud, &bank->pull); + + bank++; + ge++; + } +} + +#ifdef CONFIG_LCD +struct s6e63m0_platform_data { + struct s5pc1xx_gpio_bank *bank; + unsigned int num; +}; + +extern void s6e63m0_set_spi_interface(struct s6e63m0_platform_data *cs, + struct s6e63m0_platform_data *clk, struct s6e63m0_platform_data *si, + struct s6e63m0_platform_data *so); + +struct s6e63m0_platform_data pd_cs, pd_clk, pd_si, pd_so; +struct s5pc110_gpio *gpio_base = (struct s5pc110_gpio *) S5PC110_GPIO_BASE; + +void lcd_cfg_gpio(void) +{ + unsigned int i, f3_end = 4; + + for (i = 0; i < 8; i++) { + /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */ + gpio_cfg_pin(&gpio_base->gpio_f0, i, GPIO_FUNC(2)); + gpio_cfg_pin(&gpio_base->gpio_f1, i, GPIO_FUNC(2)); + gpio_cfg_pin(&gpio_base->gpio_f2, i, GPIO_FUNC(2)); + /* pull-up/down disable */ + gpio_set_pull(&gpio_base->gpio_f0, i, GPIO_PULL_NONE); + gpio_set_pull(&gpio_base->gpio_f1, i, GPIO_PULL_NONE); + gpio_set_pull(&gpio_base->gpio_f2, i, GPIO_PULL_NONE); + + /* drive strength to max (24bit) */ + gpio_set_drv(&gpio_base->gpio_f0, i, GPIO_DRV_4x); + gpio_set_rate(&gpio_base->gpio_f0, i, GPIO_DRV_SLOW); + gpio_set_drv(&gpio_base->gpio_f1, i, GPIO_DRV_4x); + gpio_set_rate(&gpio_base->gpio_f1, i, GPIO_DRV_SLOW); + gpio_set_drv(&gpio_base->gpio_f2, i, GPIO_DRV_4x); + gpio_set_rate(&gpio_base->gpio_f2, i, GPIO_DRV_SLOW); + } + + /* set DISPLAY_DE_B pin for dual rgb mode. */ + if (board_is_media()) + f3_end = 5; + + for (i = 0; i < f3_end; i++) { + /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */ + gpio_cfg_pin(&gpio_base->gpio_f3, i, GPIO_PULL_UP); + /* pull-up/down disable */ + gpio_set_pull(&gpio_base->gpio_f3, i, GPIO_PULL_NONE); + /* drive strength to max (24bit) */ + gpio_set_drv(&gpio_base->gpio_f3, i, GPIO_DRV_4x); + gpio_set_rate(&gpio_base->gpio_f3, i, GPIO_DRV_SLOW); + } + /* display output path selection (only [1:0] valid) */ + writel(0x2, 0xE0107008); + + /* gpio pad configuration for LCD reset. */ + gpio_cfg_pin(&gpio_base->gpio_mp0_5, 5, GPIO_OUTPUT); + + /* gpio pad configuration for LCD ON. */ + gpio_cfg_pin(&gpio_base->gpio_j1, 3, GPIO_OUTPUT); + + /* MLCD_ON2 */ + + if (board_is_p2_real()) + gpio_cfg_pin(&gpio_base->gpio_j1, 4, GPIO_OUTPUT); + else + gpio_cfg_pin(&gpio_base->gpio_j2, 6, GPIO_OUTPUT); + + /* LCD_BACKLIGHT_EN */ + if (machine_is_geminus()) + gpio_cfg_pin(&gpio_base->gpio_mp0_5, 0, GPIO_OUTPUT); + + /* + * gpio pad configuration for + * DISPLAY_CS, DISPLAY_CLK, DISPLAY_SO, DISPLAY_SI. + */ + gpio_cfg_pin(&gpio_base->gpio_mp0_1, 1, GPIO_OUTPUT); + gpio_cfg_pin(&gpio_base->gpio_mp0_4, 1, GPIO_OUTPUT); + gpio_cfg_pin(&gpio_base->gpio_mp0_4, 2, GPIO_INPUT); + gpio_cfg_pin(&gpio_base->gpio_mp0_4, 3, GPIO_OUTPUT); + + if (machine_is_aquila()) { + pd_cs.bank = &gpio_base->gpio_mp0_1; + pd_cs.num = 1; + pd_clk.bank = &gpio_base->gpio_mp0_4; + pd_clk.num = 1; + pd_si.bank = &gpio_base->gpio_mp0_4; + pd_si.num = 3; + pd_so.bank = &gpio_base->gpio_mp0_4; + pd_so.num = 2; + + /* these data would be sent to s6e63m0 lcd panel driver. */ + //s6e63m0_set_spi_interface(&pd_cs, &pd_clk, &pd_si, &pd_so); + } + + if (machine_is_cypress()) { + /* FLCD_CS */ + gpio_cfg_pin(&gpio_base->gpio_mp0_1, 0, GPIO_OUTPUT); + /* FLCD_CLK */ + gpio_cfg_pin(&gpio_base->gpio_mp0_4, 0, GPIO_OUTPUT); + /* FLCD_SDI */ + gpio_cfg_pin(&gpio_base->gpio_mp0_4, 2, GPIO_OUTPUT); + /* FLCD_RST_S */ + gpio_cfg_pin(&gpio_base->gpio_mp0_4, 5, GPIO_OUTPUT); + /* FLCD_ON_S */ + gpio_cfg_pin(&gpio_base->gpio_g2, 2, GPIO_OUTPUT); + + pd_cs.bank = &gpio_base->gpio_mp0_1; + pd_cs.num = 0; + pd_clk.bank = &gpio_base->gpio_mp0_4; + pd_clk.num = 0; + pd_si.bank = &gpio_base->gpio_mp0_4; + pd_si.num = 2; + + /* these data would be sent to s6e63m0 lcd panel driver. */ + //s6e63m0_set_spi_interface(&pd_cs, &pd_clk, &pd_si, NULL); + } + + return; +} + +void backlight_on(unsigned int onoff) +{ + struct s5pc110_gpio *gpio = (struct s5pc110_gpio *) S5PC110_GPIO_BASE; + + if (onoff) { + if (machine_is_geminus()) + gpio_set_value(&gpio->gpio_mp0_5, 0, 1); + } else { + if (machine_is_geminus()) + gpio_set_value(&gpio->gpio_mp0_5, 0, 0); + } +} + +void reset_lcd(void) +{ + struct s5pc110_gpio *gpio = (struct s5pc110_gpio *) S5PC110_GPIO_BASE; + + if (machine_is_aquila() || machine_is_geminus()) + gpio_set_value(&gpio->gpio_mp0_5, 5, 1); + if (machine_is_cypress()) + gpio_set_value(&gpio->gpio_mp0_4, 5, 1); +} + +void lcd_power_on(unsigned int onoff) +{ + struct s5pc110_gpio *gpio = (struct s5pc110_gpio *) S5PC110_GPIO_BASE; + + if (onoff) { + if (machine_is_aquila() || machine_is_geminus()) + gpio_set_value(&gpio->gpio_j1, 3, 1); + + if (machine_is_cypress()) + gpio_set_value(&gpio->gpio_g2, 2, 1); + + if (board_is_p2_real()) + gpio_set_value(&gpio->gpio_j1, 4, 1); + else + gpio_set_value(&gpio->gpio_j2, 6, 1); + + } else { + if (machine_is_aquila() || machine_is_geminus()) + gpio_set_value(&gpio->gpio_j1, 3, 0); + + if (machine_is_cypress()) + gpio_set_value(&gpio->gpio_g2, 2, 0); + + if (board_is_p2_real()) + gpio_set_value(&gpio->gpio_j1, 4, 0); + else + gpio_set_value(&gpio->gpio_j2, 6, 0); + } +} + +extern void ams701ka_cfg_ldo(void); +extern void ams701ka_enable_ldo(unsigned int onoff); + +void init_panel_info(vidinfo_t *vid) +{ + vid->cfg_gpio = NULL; + vid->reset_lcd = NULL; + vid->backlight_on = NULL; + vid->lcd_power_on = NULL; + + vid->cfg_ldo = NULL; + vid->enable_ldo = NULL; + + vid->init_delay = 0; + vid->reset_delay = 0; + vid->power_on_delay = 0; + + vid->dual_lcd_enabled = 0; + + vid->vl_freq = 60; + vid->vl_col = 1024, + vid->vl_row = 600, + vid->vl_width = 1024, + vid->vl_height = 600, + vid->vl_clkp = CONFIG_SYS_HIGH, + vid->vl_hsp = CONFIG_SYS_HIGH, + vid->vl_vsp = CONFIG_SYS_HIGH, + vid->vl_dp = CONFIG_SYS_LOW, + vid->vl_bpix = 32, + + /* AMS701KA AMOLED Panel. */ + vid->vl_hspw = 30, + vid->vl_hbpd = 114, + vid->vl_hfpd = 48, + + vid->vl_vspw = 2, + vid->vl_vbpd = 6, + vid->vl_vfpd = 8, + + vid->cfg_gpio = lcd_cfg_gpio; + vid->reset_lcd = reset_lcd; + vid->backlight_on = backlight_on; + vid->lcd_power_on = lcd_power_on; + + vid->cfg_ldo = ams701ka_cfg_ldo; + vid->enable_ldo = ams701ka_enable_ldo; + + vid->init_delay = 25000; + vid->reset_delay = 120000; + +#if 0 + vid->vl_freq = 60; + vid->vl_col = 480, + vid->vl_row = 800, + vid->vl_width = 480, + vid->vl_height = 800, + vid->vl_clkp = CONFIG_SYS_HIGH, + vid->vl_hsp = CONFIG_SYS_LOW, + vid->vl_vsp = CONFIG_SYS_LOW, + vid->vl_dp = CONFIG_SYS_HIGH, + vid->vl_bpix = 32, + + /* tl2796 panel. */ + vid->vl_hpw = 4, + vid->vl_blw = 8, + vid->vl_elw = 8, + + vid->vl_vpw = 4, + vid->vl_bfw = 8, + vid->vl_efw = 8, +#endif +#if 0 + vid->vl_freq = 60; + vid->vl_col = 1024, + vid->vl_row = 600, + vid->vl_width = 1024, + vid->vl_height = 600, + vid->vl_clkp = CONFIG_SYS_HIGH, + vid->vl_hsp = CONFIG_SYS_HIGH, + vid->vl_vsp = CONFIG_SYS_HIGH, + vid->vl_dp = CONFIG_SYS_LOW, + vid->vl_bpix = 32, + + /* AMS701KA AMOLED Panel. */ + vid->vl_hpw = 30, + vid->vl_blw = 114, + vid->vl_elw = 48, + + vid->vl_vpw = 2, + vid->vl_bfw = 6, + vid->vl_efw = 8, +#endif +} +#endif + +static void setup_meminfo(void) +{ + char meminfo[64] = {0, }; + int count = 0, size, real; + + size = gd->bd->bi_dram[0].size >> 20; + count += sprintf(meminfo + count, "mem=%dM", size); + + /* Each Chip Select can't exceed the 256MiB */ + size = gd->bd->bi_dram[1].size >> 20; + real = min(size, 256); + count += sprintf(meminfo + count, " mem=%dM@0x%x", + real, (unsigned int)gd->bd->bi_dram[1].start); + + size -= real; + if (size > 0) { + count += sprintf(meminfo + count, " mem=%dM@0x%x", size, + (unsigned int)gd->bd->bi_dram[1].start + (real << 20)); + } + + setenv("meminfo", meminfo); +} + +int misc_init_r(void) +{ +#ifdef CONFIG_LCD + /* It should be located at first */ + lcd_is_enabled = 0; + + if (board_is_limo_real() || + board_is_limo_universal() || + board_is_j1b2()) + setenv("lcdinfo", "lcd=s6e63m0"); + /* it can't classify tl2796 with single-lcd and dual-lcd. + else + setenv("lcdinfo", "lcd=tl2796-dual"); + */ + + /* + * env values below should be added in case that lcd panel of geminus, + * p1 and p2 are enabled at u-boot. + * setenv means that lcd panel has been turned on at u-boot. + */ + if (machine_is_geminus()) + setenv("lcdinfo", "lcd=lms480jc01"); + + if (board_is_p2_real()) { + setenv("lcdinfo", "lcd=ams701"); + } else if(lcd_is_amoled()) { + setenv("lcdinfo", "lcd=ams701"); + } + +#endif + setup_meminfo(); + + show_hw_revision(); + + /* Set proper PMIC pins */ + pmic_pin_init(); + + /* Check auto burning */ + check_auto_burn(); + + /* To power up I2C2 */ + enable_ldos(); + + /* Enable T-Flash at Limo Real or Limo Universal */ + enable_t_flash(); + + /* Setup Limo Real board GPIOs */ + setup_limo_real_gpios(); + + /* Setup Media board GPIOs */ + setup_media_gpios(); + + /* Setup P1P2 board GPIOS */ + setup_p1p2_gpios(); + + /* To usbdown automatically */ + if (board_is_p2_real()) + check_p2_keypad(); + else + check_keypad(); + + /* check max8998 */ + init_pmic(); + +#ifdef CONFIG_S5PC1XXFB + display_device_info(); +#endif + + setup_power_down_mode_registers(); + + /* check max17040 */ + check_battery(); + + /* check fsa9480 */ + check_micro_usb(0); + + return 0; +} +#endif + +int board_init(void) +{ + /* Set Initial global variables */ + s5pc110_gpio = (struct s5pc110_gpio *) S5PC110_GPIO_BASE; + + gd->bd->bi_arch_number = MACH_TYPE; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + /* Check H/W Revision */ + check_hw_revision(); + + return 0; +} + +int dram_init(void) +{ + unsigned int base, memconfig0, size; + unsigned int memconfig1, sz = 0; + + if (cpu_is_s5pc100()) { + /* In mem setup, we swap the bank. So below size is correct */ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[1].start = S5PC100_PHYS_SDRAM_2; + size = 128; + } else { + /* In S5PC110, we can't swap the DMC0/1 */ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + base = S5PC110_DMC1_BASE; + /* DMC configuration */ + memconfig0 = readl(base + MEMCONFIG0_OFFSET); + gd->bd->bi_dram[1].start = memconfig0 & 0xFF000000; + + size = (memconfig0 >> 16) & 0xFF; + size = ((unsigned char) ~size) + 1; + + /* + * (0x07 + 1) * 16 = 128 MiB + * (0x0f + 1) * 16 = 256 MiB + */ + size = size << 4; + + /* + * Aquila Rev0.5 4G3G1G + * Aquila Rev0.8 4G3G1G + */ + if (machine_is_aquila() && (hwrevision(5) || hwrevision(8))) { + memconfig1 = readl(base + MEMCONFIG1_OFFSET); + + sz = (memconfig1 >> 16) & 0xFF; + sz = ((unsigned char) ~sz) + 1; + sz = sz << 4; + } + + } + /* + * bi_dram[1].size contains all DMC1 memory size + */ + gd->bd->bi_dram[1].size = (size + sz) << 20; + + return 0; +} + +/* Used for sleep test */ +static unsigned char saved_val[4][2]; +void board_sleep_init_late(void) +{ + /* CODEC_LDO_EN: GPF3[4] */ + gpio_direction_output(&s5pc110_gpio->gpio_f3, 4, 0); + /* CODEC_XTAL_EN: GPH3[2] */ + gpio_direction_output(&s5pc110_gpio->gpio_h3, 2, 0); + + /* MMC T_FLASH off */ + gpio_direction_output(&s5pc110_gpio->gpio_mp0_5, 4, 0); + /* MHL off */ + gpio_direction_output(&s5pc110_gpio->gpio_j2, 2, 0); + gpio_direction_output(&s5pc110_gpio->gpio_mp0_4, 7, 0); + gpio_direction_output(&s5pc110_gpio->gpio_j2, 3, 0); /* MHL_ON for REV02 or higher */ + + +} +void board_sleep_init(void) +{ + unsigned char addr; + unsigned char val[2]; + + i2c_set_bus_num(I2C_PMIC); + addr = 0xCC >> 1; + if (i2c_probe(addr)) { + printf("Can't find max8998\n"); + return; + } + + /* Set ONOFF1 */ + i2c_read(addr, MAX8998_REG_ONOFF1, 1, val, 1); + saved_val[0][0] = val[0]; + saved_val[0][1] = val[1]; + val[0] &= ~((1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | + (1 << 1) | (1 << 0)); + i2c_write(addr, MAX8998_REG_ONOFF1, 1, val, 1); + i2c_read(addr, MAX8998_REG_ONOFF1, 1, val, 1); + /* Set ONOFF2 */ + i2c_read(addr, MAX8998_REG_ONOFF2, 1, val, 1); + saved_val[1][0] = val[0]; + saved_val[1][1] = val[1]; + val[0] &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 3) | + (1 << 2) | (1 << 1) | (1 << 0)); + val[0] |= (1 << 7); + i2c_write(addr, MAX8998_REG_ONOFF2, 1, val, 1); + i2c_read(addr, MAX8998_REG_ONOFF2, 1, val, 1); + /* Set ONOFF3 */ + i2c_read(addr, MAX8998_REG_ONOFF3, 1, val, 1); + saved_val[2][0] = val[0]; + saved_val[2][1] = val[1]; + val[0] &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4)); + i2c_write(addr, MAX8998_REG_ONOFF3, 1, val, 1); + i2c_read(addr, MAX8998_REG_ONOFF3, 1, val, 1); + /* Set ONOFF4 */ + i2c_read(addr, MAX8998_REG_ONOFF3+1, 1, val, 1); + saved_val[3][0] = val[0]; + saved_val[3][1] = val[1]; + val[0] &= ~((1 << 7) | (1 << 6) | (1 << 4)); + i2c_write(addr, MAX8998_REG_ONOFF3+1, 1, val, 1); + i2c_read(addr, MAX8998_REG_ONOFF3+1, 1, val, 1); + printf("Turned off regulators. Preparing to sleep. [%s:%d]\n", + __FILE__, __LINE__); +} + +void board_sleep_resume(void) +{ + unsigned char addr; + unsigned char val[2]; + + show_hw_revision(); + + i2c_set_bus_num(I2C_PMIC); + addr = 0xCC >> 1; + if (i2c_probe(addr)) { + printf("Can't find max8998\n"); + return; + } + + /* Set ONOFF1 */ + i2c_write(addr, MAX8998_REG_ONOFF1, 1, saved_val[0], 1); + i2c_read(addr, MAX8998_REG_ONOFF1, 1, val, 1); + /* Set ONOFF2 */ + i2c_write(addr, MAX8998_REG_ONOFF2, 1, saved_val[1], 1); + i2c_read(addr, MAX8998_REG_ONOFF2, 1, val, 1); + /* Set ONOFF3 */ + i2c_write(addr, MAX8998_REG_ONOFF3, 1, saved_val[2], 1); + i2c_read(addr, MAX8998_REG_ONOFF3, 1, val, 1); + /* Set ONOFF4 */ + i2c_write(addr, MAX8998_REG_ONOFF3+1, 1, saved_val[3], 1); + i2c_read(addr, MAX8998_REG_ONOFF3+1, 1, val, 1); + printf("Waked up.\n"); + + /* check max17040 */ + check_battery(); + + /* check fsa9480 */ + check_micro_usb(1); +} + +#ifdef CONFIG_CMD_USBDOWN +int usb_board_init(void) +{ +#ifdef CONFIG_CMD_PMIC + run_command("pmic ldo 3 on", 0); +#endif + + if (cpu_is_s5pc100()) { +#ifdef CONFIG_HARD_I2C + uchar val[2] = {0,}; + + /* PMIC */ + if (i2c_read(0x66, 0, 1, val, 2)) { + printf("i2c_read error\n"); + return 1; + } + + val[0] |= (1 << 3); + val[1] |= (1 << 5); + + if (i2c_write(0x66, 0, 1, val, 2)) { + printf("i2c_write error\n"); + return 1; + } + i2c_read(0x66, 0, 1, val, 2); +#endif + return 0; + } + + /* S5PC110 */ + if (board_is_limo_universal() || + board_is_limo_real() || + board_is_media()) { + /* check usb path */ + if (board_is_limo_real() && !hwrevision(6)) + check_mhl(); + } + + if (machine_is_tickertape()) + /* USB_SEL: XM0ADDR_0: MP04[0] output mode */ + gpio_direction_output(&s5pc110_gpio->gpio_mp0_4, 0, 0); + + return 0; +} +#endif + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + unsigned int reg; + unsigned int clock; + struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + int i; + + /* MMC0 Clock source = SCLKMPLL */ + reg = readl(&clk->src4); + reg &= ~0xf; + reg |= 0x6; + writel(reg, &clk->src4); + + reg = readl(&clk->div4); + reg &= ~0xf; + + /* set div value near 50MHz */ + clock = get_pll_clk(MPLL) / 1000000; + for (i = 0; i < 0xf; i++) { + if ((clock / (i + 1)) <= 50) { + reg |= i << 0; + break; + } + } + + writel(reg, &clk->div4); + + /* + * MMC0 GPIO + * GPG0[0] SD_0_CLK + * GPG0[1] SD_0_CMD + * GPG0[2] SD_0_CDn -> Not used + * GPG0[3:6] SD_0_DATA[0:3] + */ + for (i = 0; i < 7; i++) { + if (i == 2) + continue; + /* GPG0[0:6] special function 2 */ + gpio_cfg_pin(&s5pc110_gpio->gpio_g0, i, 0x2); + /* GPG0[0:6] pull disable */ + gpio_set_pull(&s5pc110_gpio->gpio_g0, i, GPIO_PULL_NONE); + /* GPG0[0:6] drv 4x */ + gpio_set_drv(&s5pc110_gpio->gpio_g0, i, GPIO_DRV_4x); + } + + return s5pc1xx_mmc_init(0); +} +#endif + +#ifdef CONFIG_CMD_PMIC +static int pmic_status(void) +{ + unsigned char addr, val[2]; + int reg, i; + + i2c_set_bus_num(I2C_PMIC); + addr = 0xCC >> 1; + if (i2c_probe(addr)) { + printf("Can't found max8998\n"); + return -1; + } + + reg = 0x11; + i2c_read(addr, reg, 1, val, 1); + for (i = 7; i >= 4; i--) + printf("BUCK%d %s\n", 7 - i + 1, + val[0] & (1 << i) ? "on" : "off"); + for (; i >= 0; i--) + printf("LDO%d %s\n", 5 - i, + val[0] & (1 << i) ? "on" : "off"); + reg = 0x12; + i2c_read(addr, reg, 1, val, 1); + for (i = 7; i >= 0; i--) + printf("LDO%d %s\n", 7 - i + 6, + val[0] & (1 << i) ? "on" : "off"); + reg = 0x13; + i2c_read(addr, reg, 1, val, 1); + for (i = 7; i >= 4; i--) + printf("LDO%d %s\n", 7 - i + 14, + val[0] & (1 << i) ? "on" : "off"); + return 0; +} + +static int pmic_ldo_control(int buck, int ldo, int on) +{ + unsigned char addr, val[2]; + unsigned int reg, shift; + + if (ldo) { + if (ldo < 2) + return -1; + if (ldo <= 5) { + reg = 0x11; + shift = 5 - ldo; + } else if (ldo <= 13) { + reg = 0x12; + shift = 13 - ldo; + } else if (ldo <= 17) { + reg = 0x13; + shift = 17 - ldo + 4; + } else + return -1; + } else if (buck) { + if (buck > 4) + return -1; + reg = 0x11; + shift = 4 - buck + 4; + } else + return -1; + + i2c_set_bus_num(I2C_PMIC); + addr = 0xCC >> 1; + if (i2c_probe(addr)) { + printf("Can't found max8998\n"); + return -1; + } + + i2c_read(addr, reg, 1, val, 1); + if (on) + val[0] |= (1 << shift); + else + val[0] &= ~(1 << shift); + i2c_write(addr, reg, 1, val, 1); + i2c_read(addr, reg, 1, val, 1); + printf("%s %d value 0x%x, %s\n", buck ? "buck" : "ldo", buck ? : ldo, + val[0], val[0] & (1 << shift) ? "on" : "off"); + + return 0; +} + +static int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int buck = 0, ldo = 0, on = -1; + + switch (argc) { + case 2: + if (strncmp(argv[1], "status", 6) == 0) + return pmic_status(); + break; + case 4: + if (strncmp(argv[1], "ldo", 3) == 0) { + ldo = simple_strtoul(argv[2], NULL, 10); + if (strncmp(argv[3], "on", 2) == 0) + on = 1; + else if (strncmp(argv[3], "off", 3) == 0) + on = 0; + else + break; + return pmic_ldo_control(buck, ldo, on); + } + if (strncmp(argv[1], "buck", 4) == 0) { + buck = simple_strtoul(argv[2], NULL, 10); + if (strncmp(argv[3], "on", 2) == 0) + on = 1; + else if (strncmp(argv[3], "off", 3) == 0) + on = 0; + else + break; + return pmic_ldo_control(buck, ldo, on); + } + + default: + break; + } + + cmd_usage(cmdtp); + return 1; +} + +U_BOOT_CMD( + pmic, CONFIG_SYS_MAXARGS, 1, do_pmic, + "PMIC LDO & BUCK control", + "status - Display PMIC LDO & BUCK status\n" + "pmic ldo num on/off - Turn on/off the LDO\n" + "pmic buck num on/off - Turn on/off the BUCK\n" +); +#endif + +#ifdef CONFIG_CMD_DEVICE_POWER + +enum { + POWER_NONE, + POWER_TOUCH, + POWER_3_TOUCHKEY, + POWER_LCD, + POWER_HAPTIC, + POWER_AUDIO_CODEC, + POWER_FM_RADIO, + POWER_BT_WIFI, + POWER_HDMI, +}; + +static void power_display_devices(void) +{ + printf("devices:\n"); + printf("\t%d - touch\n", POWER_TOUCH); + printf("\t%d - 3 touchkey\n", POWER_3_TOUCHKEY); + printf("\t%d - LCD\n", POWER_LCD); + printf("\t%d - Haptic\n", POWER_HAPTIC); + printf("\t%d - Audio Codec\n", POWER_AUDIO_CODEC); + printf("\t%d - FM Radio\n", POWER_FM_RADIO); + printf("\t%d - BT/WiFi\n", POWER_BT_WIFI); + printf("\t%d - HDMI\n", POWER_HDMI); +} + +static int power_hdmi(int on) +{ + /* HDMI_EN1: GPJ2[2] */ + gpio_direction_output(&s5pc110_gpio->gpio_j2, 2, on); + /* MHL_ON: GPJ2[3] */ + gpio_direction_output(&s5pc110_gpio->gpio_j2, 3, on); + return 0; +} + +static int power_bt_wifi(int on) +{ + /* WLAN_BT_EN: GPB[5] */ + gpio_direction_output(&s5pc110_gpio->gpio_b, 5, on); + return 0; +} + +static int power_fm_radio(int on) +{ + /* FM_BUS_nRST: GPJ2[5] */ + gpio_direction_output(&s5pc110_gpio->gpio_j2, 5, !on); + return 0; +} + +static int power_audio_codec(int on) +{ + /* CODEC_LDO_EN: GPF3[4] */ + gpio_direction_output(&s5pc110_gpio->gpio_f3, 4, on); + /* CODEC_XTAL_EN: GPH3[2] */ + gpio_direction_output(&s5pc110_gpio->gpio_h3, 2, on); + return 0; +} + +static int power_haptic(int on) +{ + /* HAPTIC_ON: GPJ1[1] */ + gpio_direction_output(&s5pc110_gpio->gpio_j1, 1, on); + return 0; +} + +static int power_lcd(int on) +{ + /* MLCD_ON: GPJ1[3] */ + gpio_direction_output(&s5pc110_gpio->gpio_j1, 3, on); + return 0; +} + +static int power_touch(int on) +{ + /* TOUCH_EN: GPG3[6] */ + gpio_direction_output(&s5pc110_gpio->gpio_g3, 6, on); + return 0; +} + +static int power_3_touchkey(int on) +{ + if (on) { + /* 3_TOUCH_EN - GPJ3[0] : (J1B2) */ + /* 3_TOUCH_EN - GPJ3[5] : (not J1B2) */ + if (board_rev & J1_B2_BOARD) + gpio_direction_output(&s5pc110_gpio->gpio_j3, 0, on); + else + gpio_direction_output(&s5pc110_gpio->gpio_j3, 5, on); + + /* 3_TOUCH_CE - GPJ2[6] */ + gpio_direction_output(&s5pc110_gpio->gpio_j2, 6, on); /* TOUCH_CE */ + } else { + /* 3_TOUCH_CE - GPJ2[6] */ + gpio_direction_output(&s5pc110_gpio->gpio_j2, 6, on); /* TOUCH_CE */ + } + + if (on) { + unsigned int reg; + unsigned char val[2]; + unsigned char addr = 0x20; /* mcs5000 3-touchkey */ + + /* Require 100ms */ + udelay(80 * 1000); + + /* 3 touchkey */ + i2c_set_bus_num(I2C_GPIO6); + + /* Workaround to probe */ + if (i2c_probe(addr)) { + if (i2c_probe(addr)) { + printf("Can't found 3 touchkey\n"); + return -ENODEV; + } + } + +#define MCS5000_TK_HW_VERSION 0x06 +#define MCS5000_TK_FW_VERSION 0x0A +#define MCS5000_TK_MI_VERSION 0x0B + + reg = MCS5000_TK_MI_VERSION; + i2c_read(addr, reg, 1, val, 1); + printf("3-touchkey:\tM/I 0x%x, ", val[0]); + reg = MCS5000_TK_HW_VERSION; + i2c_read(addr, reg, 1, val, 1); + printf("H/W 0x%x, ", val[0]); + reg = MCS5000_TK_FW_VERSION; + i2c_read(addr, reg, 1, val, 1); + printf("F/W 0x%x\n", val[0]); + } + return 0; +} + +static int power_control(int device, int on) +{ + switch (device) { + case POWER_TOUCH: + return power_touch(on); + case POWER_3_TOUCHKEY: + return power_3_touchkey(on); + case POWER_LCD: + return power_lcd(on); + case POWER_HAPTIC: + return power_haptic(on); + case POWER_AUDIO_CODEC: + return power_audio_codec(on); + case POWER_FM_RADIO: + return power_fm_radio(on); + case POWER_BT_WIFI: + return power_bt_wifi(on); + case POWER_HDMI: + return power_hdmi(on); + default: + printf("I don't know device %d\n", device); + break; + } + return 0; +} + +static int power_on(int on) +{ + power_touch(on); + power_3_touchkey(on); + power_lcd(on); + power_haptic(on); + power_audio_codec(on); + power_fm_radio(on); + power_bt_wifi(on); + power_hdmi(on); + + return 0; +} + +static int do_power(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int device, on; + + if (!machine_is_aquila()) + goto out; + + switch (argc) { + case 2: + if (strncmp(argv[1], "on", 2) == 0) + return power_on(1); + if (strncmp(argv[1], "off", 3) == 0) + return power_on(0); + break; + case 3: + device = simple_strtoul(argv[1], NULL, 10); + if (device < 0) + break; + + if (strncmp(argv[2], "on", 2) == 0) + on = 1; + else if (strncmp(argv[2], "off", 3) == 0) + on = 0; + else + break; + return power_control(device, on); + default: + break; + } +out: + cmd_usage(cmdtp); + power_display_devices(); + return 1; +} + +U_BOOT_CMD( + power, CONFIG_SYS_MAXARGS, 1, do_power, + "Device Power Management control", + "device on/off - Turn on/off the device\n" +); +#endif diff --git a/board/samsung/p1p2/psi_ram.h b/board/samsung/p1p2/psi_ram.h new file mode 100644 index 0000000..a9da4a0 --- /dev/null +++ b/board/samsung/p1p2/psi_ram.h @@ -0,0 +1,941 @@ +unsigned char g_tblBin[] = +{ + 0x87, 0x0d, 0x00, 0xea, 0x6c, 0x69, 0x48, 0x55, 0x01, 0xa0, 0xfe, 0xfd, 0x07, 0x00, 0x01, 0x00, + 0x00, 0xff, 0x00, 0x00, 0x10, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xfe, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x08, 0x00, 0xff, 0xff, 0xf7, 0xff, 0x00, 0x02, 0x08, 0x00, 0x43, 0x4a, 0x4b, 0x54, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 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