From: Vladimir Murzin Date: Mon, 24 Apr 2017 09:40:48 +0000 (+0100) Subject: ARM: 8670/1: V7M: Do not corrupt vector table around v7m_invalidate_l1 call X-Git-Tag: v4.14-rc1~965^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6d80594936914e798b1b54b3bfe4bd68d8418966;p=platform%2Fkernel%2Flinux-rpi.git ARM: 8670/1: V7M: Do not corrupt vector table around v7m_invalidate_l1 call We save/restore registers around v7m_invalidate_l1 to address pointed by r12, which is vector table, so the first eight entries are overwritten with a garbage. We already have stack setup at that stage, so use it to save/restore register. Fixes: 6a8146f420be ("ARM: 8609/1: V7M: Add support for the Cortex-M7 processor") Cc: Signed-off-by: Vladimir Murzin Signed-off-by: Russell King --- diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index 8dea616..5049777 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S @@ -147,10 +147,10 @@ __v7m_setup_cont: @ Configure caches (if implemented) teq r8, #0 - stmneia r12, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6 + stmneia sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6 blne v7m_invalidate_l1 teq r8, #0 @ re-evalutae condition - ldmneia r12, {r0-r6, lr} + ldmneia sp, {r0-r6, lr} @ Configure the System Control Register to ensure 8-byte stack alignment @ Note the STKALIGN bit is either RW or RAO.