From: Mugunthan V N Date: Tue, 18 Jun 2013 09:34:35 +0000 (+0530) Subject: drivers: net: cpsw: fix cpsw clock gating issue across suspend/resume X-Git-Tag: upstream/snapshot3+hdmi~4870^2~31 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6d3d76f877ca061911343d5d1650458906fdf0ea;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git drivers: net: cpsw: fix cpsw clock gating issue across suspend/resume Due to some hardware integration issue, CPSW sliver modules requires a reset across suspend/resume cycle for a successful clock gating to CPGMAC (CPSW and Davinci MDIO) in AM335x PG1.0. This issue is fixed in PG2.x, though to support suspend/resume on PG1.0 this reset is required. Signed-off-by: Mugunthan V N Signed-off-by: David S. Miller --- diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 2fd69db..e66a202 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1976,6 +1976,8 @@ static int cpsw_suspend(struct device *dev) if (netif_running(ndev)) cpsw_ndo_stop(ndev); + soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset); + soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset); pm_runtime_put_sync(&pdev->dev); return 0;