From: Chen-Yu Tsai Date: Sat, 5 Dec 2015 13:16:42 +0000 (+0800) Subject: clk: sunxi: Add DRAM gates support for sun4i-a10 X-Git-Tag: v4.14-rc1~4001^2~9^2~5 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6d3a47c29186aa8d26ff05a6209c94291ace0696;p=platform%2Fkernel%2Flinux-rpi.git clk: sunxi: Add DRAM gates support for sun4i-a10 The A10/A20 share the same set of DRAM clock gates, which controls direct memory access for some peripherals. On the A10, bit 15 controls the system's DRAM clock output (possibly to the DRAM chips), which we need to keep on. On the A20 this has been moved to the DRAM controller, becoming a no-op. However it is still listed in the user manual, so add it anyway. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 153ac72..ef0b452 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -57,6 +57,7 @@ Required properties: "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80 + "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10 "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 "allwinner,sun4i-a10-mmc-clk" - for the MMC clock "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c index c8acc06..f4da52b 100644 --- a/drivers/clk/sunxi/clk-simple-gates.c +++ b/drivers/clk/sunxi/clk-simple-gates.c @@ -160,3 +160,15 @@ CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk", sun4i_a10_ahb_init); CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk", sun4i_a10_ahb_init); + +static const int sun4i_a10_dram_critical_clocks[] __initconst = { + 15, /* dram_output */ +}; + +static void __init sun4i_a10_dram_init(struct device_node *node) +{ + sunxi_simple_gates_setup(node, sun4i_a10_dram_critical_clocks, + ARRAY_SIZE(sun4i_a10_dram_critical_clocks)); +} +CLK_OF_DECLARE(sun4i_a10_dram, "allwinner,sun4i-a10-dram-gates-clk", + sun4i_a10_dram_init);