From: Craig Topper Date: Tue, 27 Dec 2022 17:41:29 +0000 (-0800) Subject: [RISCV] Use SmallVector::append to replace some for loops in intrinsic creation. NFC X-Git-Tag: upstream/17.0.6~22563 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6d323e7e51c6a58b44b6b1a982bbda7edfd962fb;p=platform%2Fupstream%2Fllvm.git [RISCV] Use SmallVector::append to replace some for loops in intrinsic creation. NFC Reviewed By: eopXD Differential Revision: https://reviews.llvm.org/D140678 --- diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index 2669df0..9c05d893 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -853,8 +853,7 @@ multiclass RVVUnitStridedSegLoad { Operands.push_back(Ops[NF]); Operands.push_back(Ops[NF + 2]); } else { - for (unsigned I = 0; I < NF; ++I) - Operands.push_back(Ops[NF + I + 1]); + Operands.append(Ops.begin() + NF + 1, Ops.begin() + 2 * NF + 1); Operands.push_back(Ops[2 * NF + 1]); Operands.push_back(Ops[NF]); Operands.push_back(Ops[2 * NF + 2]); @@ -870,10 +869,7 @@ multiclass RVVUnitStridedSegLoad { Operands.push_back(Ops[NF]); Operands.push_back(Ops[NF + 1]); } else { - for (unsigned I = 0; I < NF; ++I) - Operands.push_back(Ops[NF + I]); - Operands.push_back(Ops[2 * NF]); - Operands.push_back(Ops[2 * NF + 1]); + Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF + 2); } } llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); @@ -931,8 +927,7 @@ multiclass RVVUnitStridedSegLoadFF { Operands.push_back(Ops[NF + 3]); NewVL = Ops[NF + 2]; } else { - for (unsigned I = 0; I < NF; ++I) - Operands.push_back(Ops[NF + I + 1]); + Operands.append(Ops.begin() + NF + 1, Ops.begin() + 2 * NF + 1); Operands.push_back(Ops[2 * NF + 1]); Operands.push_back(Ops[NF]); Operands.push_back(Ops[2 * NF + 3]); @@ -950,8 +945,7 @@ multiclass RVVUnitStridedSegLoadFF { Operands.push_back(Ops[NF + 2]); NewVL = Ops[NF + 1]; } else { - for (unsigned I = 0; I < NF; ++I) - Operands.push_back(Ops[NF + I]); + Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF); Operands.push_back(Ops[2 * NF]); Operands.push_back(Ops[2 * NF + 2]); NewVL = Ops[2 * NF + 1]; @@ -1012,8 +1006,7 @@ multiclass RVVStridedSegLoad { Operands.push_back(Ops[NF]); Operands.push_back(Ops[NF + 3]); } else { - for (unsigned I = 0; I < NF; ++I) - Operands.push_back(Ops[NF + I + 1]); + Operands.append(Ops.begin() + NF + 1, Ops.begin() + 2 * NF + 1); Operands.push_back(Ops[2 * NF + 1]); Operands.push_back(Ops[2 * NF + 2]); Operands.push_back(Ops[NF]); @@ -1031,8 +1024,7 @@ multiclass RVVStridedSegLoad { Operands.push_back(Ops[NF + 1]); Operands.push_back(Ops[NF + 2]); } else { - for (unsigned I = 0; I < NF; ++I) - Operands.push_back(Ops[NF + I]); + Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF); Operands.push_back(Ops[2 * NF]); Operands.push_back(Ops[2 * NF + 1]); Operands.push_back(Ops[2 * NF + 2]); @@ -1087,8 +1079,7 @@ multiclass RVVIndexedSegLoad { Operands.push_back(Ops[NF + 3]); IntrinsicTypes = {ResultType, Ops[NF + 2]->getType(), Ops.back()->getType()}; } else { - for (unsigned I = 0; I < NF; ++I) - Operands.push_back(Ops[NF + I + 1]); + Operands.append(Ops.begin() + NF + 1, Ops.begin() + 2 * NF + 1); Operands.push_back(Ops[2 * NF + 1]); Operands.push_back(Ops[2 * NF + 2]); Operands.push_back(Ops[NF]); @@ -1108,8 +1099,7 @@ multiclass RVVIndexedSegLoad { Operands.push_back(Ops[NF + 2]); IntrinsicTypes = {ResultType, Ops[NF + 1]->getType(), Ops.back()->getType()}; } else { - for (unsigned I = 0; I < NF; ++I) - Operands.push_back(Ops[NF + I]); + Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF); Operands.push_back(Ops[2 * NF]); Operands.push_back(Ops[2 * NF + 1]); Operands.push_back(Ops[2 * NF + 2]);