From: Nikita Yushchenko Date: Mon, 28 Apr 2014 15:23:44 +0000 (+0400) Subject: fsl-usb: do not test for PHY_CLK_VALID bit on controller version 1.6 X-Git-Tag: upstream/snapshot3+hdmi~2712 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6cb00d58ad0724088646dc1fec20de4e7bbaaf72;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git fsl-usb: do not test for PHY_CLK_VALID bit on controller version 1.6 commit d183c81929beeba842b74422f754446ef2b8b49c upstream. Per reference manuals of Freescale P1020 and P2020 SoCs, USB controller present in these SoCs has bit 17 of USBx_CONTROL register marked as Reserved - there is no PHY_CLK_VALID bit there. Testing for this bit in ehci_fsl_setup_phy() behaves differently on two P1020RDB boards available here - on one board test passes and fsl-usb init succeeds, but on other board test fails, causing fsl-usb init to fail. This patch changes ehci_fsl_setup_phy() not to test PHY_CLK_VALID on controller version 1.6 that (per manual) does not have this bit. Signed-off-by: Nikita Yushchenko Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 6f2c8d3..cf2734b 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -248,7 +248,8 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, break; } - if (pdata->have_sysif_regs && pdata->controller_ver && + if (pdata->have_sysif_regs && + pdata->controller_ver > FSL_USB_VER_1_6 && (phy_mode == FSL_USB2_PHY_ULPI)) { /* check PHY_CLK_VALID to get phy clk valid */ if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &