From: Eric Anholt <eric@anholt.net>
Date: Wed, 30 Nov 2016 20:19:38 +0000 (-0800)
Subject: vc4: Try to schedule QIR instructions between writing to and reading math.
X-Git-Tag: upstream/17.1.0~4161
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6c34084d8eafff3a764cd1ad49afacd211470f7b;p=platform%2Fupstream%2Fmesa.git

vc4: Try to schedule QIR instructions between writing to and reading math.

This helps us get the delay slots between SFU writes and reads filled.

total instructions in shared programs: 94494 -> 93970 (-0.55%)
instructions in affected programs:     59206 -> 58682 (-0.89%)

3DMMES performance +1.89967% +/- 0.157611% (n=10,9)
---

diff --git a/src/gallium/drivers/vc4/vc4_qir_schedule.c b/src/gallium/drivers/vc4/vc4_qir_schedule.c
index ea48a85..89e6d1d 100644
--- a/src/gallium/drivers/vc4/vc4_qir_schedule.c
+++ b/src/gallium/drivers/vc4/vc4_qir_schedule.c
@@ -569,6 +569,28 @@ latency_between(struct schedule_node *before, struct schedule_node *after)
             after->inst->op == QOP_TEX_RESULT)
                 return 100;
 
+        switch (before->inst->op) {
+        case QOP_RCP:
+        case QOP_RSQ:
+        case QOP_EXP2:
+        case QOP_LOG2:
+                for (int i = 0; i < qir_get_nsrc(after->inst); i++) {
+                        if (after->inst->src[i].file ==
+                            before->inst->dst.file &&
+                            after->inst->src[i].index ==
+                            before->inst->dst.index) {
+                                /* There are two QPU delay slots before we can
+                                 * read a math result, which could be up to 4
+                                 * QIR instructions if they packed well.
+                                 */
+                                return 4;
+                        }
+                }
+                break;
+        default:
+                break;
+        }
+
         return 1;
 }