From: Eugene Leviant <eleviant@accesssoftek.com>
Date: Tue, 21 Nov 2017 11:01:28 +0000 (+0000)
Subject: [MI scheduler] Fix VADD and VSUB in cortex-a57 model
X-Git-Tag: llvmorg-6.0.0-rc1~2920
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6bc35a93e6be166ec25cc42ab081ea161740ba3b;p=platform%2Fupstream%2Fllvm.git

[MI scheduler] Fix VADD and VSUB in cortex-a57 model

This patch fixes instregex for interger vector add/sub instructions

Differential revision: https://reviews.llvm.org/D40254

llvm-svn: 318749
---

diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
index 525079d..1ed9e14 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -971,9 +971,9 @@ def : InstRW<[A57WriteVABAL, A57ReadVABAL], (instregex "VABAL(s|u)")>;
 def : InstRW<[A57Write_3cyc_1V], (instregex "VABDL(s|u)")>;
 
 // ASIMD arith, basic
-def : InstRW<[A57Write_3cyc_1V], (instregex "VADD", "VADDL", "VADDW",
+def : InstRW<[A57Write_3cyc_1V], (instregex "VADDv", "VADDL", "VADDW",
   "VNEG(s8d|s16d|s32d|s8q|s16q|s32q|d|q)",
-  "VPADDi", "VPADDL", "VSUB", "VSUBL", "VSUBW")>;
+  "VPADDi", "VPADDL", "VSUBv", "VSUBL", "VSUBW")>;
 
 // ASIMD arith, complex
 def : InstRW<[A57Write_3cyc_1V], (instregex "VABS", "VADDHN", "VHADD", "VHSUB",
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vadd.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vadd.ll
new file mode 100644
index 0000000..eb8d1c8
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vadd.ll
@@ -0,0 +1,26 @@
+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+
+; CHECK-LABEL:  addv_i32:BB#0
+; CHECK:        SU(8): {{.*}} VADDv4i32
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 3
+
+define <4 x i32> @addv_i32(<4 x i32>, <4 x i32>) {
+  %3 = add <4 x i32> %1, %0
+  ret <4 x i32> %3
+}
+
+; CHECK-LABEL:  addv_f32:BB#0
+; CHECK:        SU(8): {{.*}} VADDfq
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 5
+
+define <4 x float> @addv_f32(<4 x float>, <4 x float>) {
+  %3 = fadd <4 x float> %0, %1
+  ret <4 x float> %3
+}
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vsub.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vsub.ll
new file mode 100644
index 0000000..c3c445d
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vsub.ll
@@ -0,0 +1,26 @@
+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+
+; CHECK-LABEL:  subv_i32:BB#0
+; CHECK:        SU(8): {{.*}} VSUBv4i32
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 3
+
+define <4 x i32> @subv_i32(<4 x i32>, <4 x i32>) {
+  %3 = sub <4 x i32> %1, %0
+  ret <4 x i32> %3
+}
+
+; CHECK-LABEL:  subv_f32:BB#0
+; CHECK:        SU(8): {{.*}} VSUBfq
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 5
+
+define <4 x float> @subv_f32(<4 x float>, <4 x float>) {
+  %3 = fsub <4 x float> %0, %1
+  ret <4 x float> %3
+}