From: Grygorii Strashko Date: Mon, 18 Nov 2019 12:20:16 +0000 (+0200) Subject: ARM: dts: dra7: fix cpsw mdio fck clock X-Git-Tag: v5.15~4939^2~5^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6af0a549c25e0d02366aa95507bfe3cad2f7b68b;p=platform%2Fkernel%2Flinux-starfive.git ARM: dts: dra7: fix cpsw mdio fck clock The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0) is specified incorrectly, which is caused incorrect MDIO bus clock configuration MDCLK. The correct CPSW MDIO functional clock is gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it. Fixes: 1faa415c9c6e ("ARM: dts: Add fck for cpsw mdio for omap variants") Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index ea0e7c1..be5c505 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -3065,7 +3065,7 @@ davinci_mdio: mdio@1000 { compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; + clocks = <&gmac_main_clk>; clock-names = "fck"; #address-cells = <1>; #size-cells = <0>;