From: Palmer Dabbelt <palmer@rivosinc.com>
Date: Mon, 21 Mar 2022 23:07:12 +0000 (-0700)
Subject: perf: RISC-V: Add support for SBI PMU and Sscofpmf
X-Git-Tag: v6.1-rc5~1731^2~1
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6ae1af9ca0e81f7123d36eae9bf25de63722fbf6;p=platform%2Fkernel%2Flinux-starfive.git

perf: RISC-V: Add support for SBI PMU and Sscofpmf

This series improves perf support for RISC-V based system using SBI PMU
and Sscofpmf extensions, by adding a new generic RISC-V perf framework
along with a pair of drivers: one that usese the new
performance-monitoring extensions and one that keeps support for the
existing systems that only have the legacy counters.

Tested-by: Nikita Shubin <n.shubin@yadro.com>

* palmer/riscv-pmu:
  MAINTAINERS: Add entry for RISC-V PMU drivers
  Documentation: riscv: Remove the old documentation
  RISC-V: Add sscofpmf extension support
  RISC-V: Add perf platform driver based on SBI PMU extension
  RISC-V: Add RISC-V SBI PMU extension definitions
  RISC-V: Add a simple platform driver for RISC-V legacy perf
  RISC-V: Add a perf core library for pmu drivers
  RISC-V: Add CSR encodings for all HPMCOUNTERS
  RISC-V: Remove the current perf implementation
---

6ae1af9ca0e81f7123d36eae9bf25de63722fbf6