From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Tue, 25 Apr 2023 04:31:51 +0000 (+0900)
Subject: configs: Add tizen_starfive_visionfive2 defconfig
X-Git-Tag: accepted/tizen/unified/20231106.171643~63
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6a847934a1b2cdfecb7f2e2bbf1e652bc32e94a2;p=platform%2Fkernel%2Fu-boot.git

configs: Add tizen_starfive_visionfive2 defconfig

Add tizen_starfive_visionfive2 defconfig file.
It will be used for Tizen. To maintain orignal defconfig, create a
defconfig to use tizen.

Change-Id: I361b79fb1a7c6dd2319d25a62b31ca153e26c666
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---

diff --git a/configs/tizen_starfive_visionfive2_defconfig b/configs/tizen_starfive_visionfive2_defconfig
new file mode 100644
index 0000000..550d0ff
--- /dev/null
+++ b/configs/tizen_starfive_visionfive2_defconfig
@@ -0,0 +1,79 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_SPL_TEXT_BASE=0x8000000
+CONFIG_SYS_PROMPT="StarFive #"
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_STACK=0x8180000
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000
+CONFIG_ARCH_RV64I=y
+CONFIG_CMODEL_MEDANY=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
+CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_BSS_START_ADDR=0x8040000
+CONFIG_SPL_BSS_MAX_SIZE=0x10000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x400000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_JH7110=y
+# CONFIG_I2C is not set
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_SPL_PINCONF=y
+CONFIG_SPL_PINCTRL_STARFIVE=y
+CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
+CONFIG_PINCTRL_STARFIVE=y
+# CONFIG_RAM_SIFIVE is not set
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER_EARLY=y
+CONFIG_OF_LIBFDT_OVERLAY=y