From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Fri, 15 Jun 2018 21:42:43 +0000 (+0900)
Subject: Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm/linux... 
X-Git-Tag: v5.15~8589
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6a4d4b3253c1341843ba473429cf76a0e54f053d;p=platform%2Fkernel%2Flinux-starfive.git

Merge tag 'riscv-for-linus-4.18-merge_window' of git://git./linux/kernel/git/palmer/riscv-linux

Pull RISC-V updates from Palmer Dabbelt:
 "This contains some small RISC-V updates I'd like to target for 4.18.

  They are all fairly small this time. Here's a short summary, there's
  more info in the commits/merges:

   - a fix to __clear_user to respect the passed arguments.

   - enough support for the perf subsystem to work with RISC-V's ISA
     defined performance counters.

   - support for sparse and cleanups suggested by it.

   - support for R_RISCV_32 (a relocation, not the 32-bit ISA).

   - some MAINTAINERS cleanups.

   - the addition of CONFIG_HVC_RISCV_SBI to our defconfig, as it's
     always present.

  I've given these a simple build+boot test"

* tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
  RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfig
  RISC-V: Handle R_RISCV_32 in modules
  riscv/ftrace: Export _mcount when DYNAMIC_FTRACE isn't set
  riscv: add riscv-specific predefines to CHECKFLAGS
  riscv: split the declaration of __copy_user
  riscv: no __user for probe_kernel_address()
  riscv: use NULL instead of a plain 0
  perf: riscv: Add Document for Future Porting Guide
  perf: riscv: preliminary RISC-V support
  MAINTAINERS: Update Albert's email, he's back at Berkeley
  MAINTAINERS: Add myself as a maintainer for SiFive's drivers
  riscv: Fix the bug in memory access fixup code
---

6a4d4b3253c1341843ba473429cf76a0e54f053d
diff --cc arch/riscv/Kconfig
index 42e581a,4495604..f12680c
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@@ -30,8 -22,10 +30,9 @@@ config RISC
  	select GENERIC_ATOMIC64 if !64BIT || !RISCV_ISA_A
  	select HAVE_MEMBLOCK
  	select HAVE_MEMBLOCK_NODE_MAP
 -	select HAVE_DMA_API_DEBUG
  	select HAVE_DMA_CONTIGUOUS
  	select HAVE_GENERIC_DMA_COHERENT
+ 	select HAVE_PERF_EVENTS
  	select IRQ_DOMAIN
  	select NO_BOOTMEM
  	select RISCV_ISA_A if SMP