From: yao liu <yao.liu@amlogic.com>
Date: Mon, 24 Jun 2019 09:52:21 +0000 (+0800)
Subject: dolby: fix osd1 last line abnormal [3/3]
X-Git-Tag: khadas-vims-v0.9.6-release~300
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6a166fbad738167bdcc6f31f6b9db75bdeaadaa7;p=platform%2Fkernel%2Flinux-amlogic.git

dolby: fix osd1 last line abnormal [3/3]

PD#SWPL-6807

Problem:
green line displayed when osd alpha 0xff/0x00 continuous

Solution:
close osd matrix, osd always output rgb format and
use osd1_hdr2_mat do rgb2yuv
At the same time, need disable osd1_hdr2_mtx
when dv on

Verify:
g12a/g12b/sm1

Change-Id: I1fdb11707f30a1938167b6bfc8e6ec6bce5485eb
Signed-off-by: yao liu <yao.liu@amlogic.com>
---

diff --git a/drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.c b/drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.c
index 57fa80e..828ac0e 100644
--- a/drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.c
+++ b/drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.c
@@ -3029,12 +3029,18 @@ void enable_dolby_vision(int enable)
 				else
 					VSYNC_WR_DV_REG_BITS(VPP_DOLBY_CTRL,
 						0, 3, 1);   /* bypass core3  */
-				VSYNC_WR_DV_REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL,
-					0x0);
-				VSYNC_WR_DV_REG(VPP_WRAP_OSD2_MATRIX_EN_CTRL,
-					0x0);
-				VSYNC_WR_DV_REG(VPP_WRAP_OSD3_MATRIX_EN_CTRL,
-					0x0);
+
+				if (is_meson_g12()) {
+					/*g12a/g12b/sm1: osd1 green line*/
+					enable_osd1_mtx(0);
+				} else if (is_meson_tm2_stbmode()) {
+					VSYNC_WR_DV_REG(
+					VPP_WRAP_OSD1_MATRIX_EN_CTRL, 0x0);
+					VSYNC_WR_DV_REG(
+					VPP_WRAP_OSD2_MATRIX_EN_CTRL, 0x0);
+					VSYNC_WR_DV_REG(
+					VPP_WRAP_OSD3_MATRIX_EN_CTRL, 0x0);
+				}
 				if (dolby_vision_mask & 2)
 					VSYNC_WR_DV_REG_BITS(
 						DOLBY_PATH_CTRL,
@@ -3327,12 +3333,17 @@ void enable_dolby_vision(int enable)
 				memset(&dovi_setting, 0, sizeof(dovi_setting));
 				pr_dolby_dbg("Dolby Vision STB cores turn off\n");
 			} else if (is_meson_g12() || is_meson_tm2_stbmode()) {
-				VSYNC_WR_DV_REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL,
-					0x1);
-				VSYNC_WR_DV_REG(VPP_WRAP_OSD2_MATRIX_EN_CTRL,
-					0x1);
-				VSYNC_WR_DV_REG(VPP_WRAP_OSD3_MATRIX_EN_CTRL,
-					0x1);
+				if (is_meson_g12()) {
+					/*g12a/g12b/sm1:osd1 green line*/
+					enable_osd1_mtx(1);
+				} else if (is_meson_tm2_stbmode()) {
+					VSYNC_WR_DV_REG(
+					VPP_WRAP_OSD1_MATRIX_EN_CTRL, 0x1);
+					VSYNC_WR_DV_REG(
+					VPP_WRAP_OSD2_MATRIX_EN_CTRL, 0x1);
+					VSYNC_WR_DV_REG(
+					VPP_WRAP_OSD3_MATRIX_EN_CTRL, 0x1);
+				}
 				VSYNC_WR_DV_REG_BITS(
 					DOLBY_PATH_CTRL,
 					(1 << 2) |	/* core2 bypass */