From: Sowjanya Komatineni <skomatineni@nvidia.com>
Date: Sun, 24 Mar 2019 04:45:25 +0000 (-0700)
Subject: mmc: cqhci: add CQHCI_SSC1 register CBC field mask
X-Git-Tag: v5.4-rc1~1078^2~60
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=688956440e80946e164289b23e54309bcbca7144;p=platform%2Fkernel%2Flinux-rpi.git

mmc: cqhci: add CQHCI_SSC1 register CBC field mask

This patch adds define for CBC field mask of the register
CQHCI_SSC1.

Tested-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---

diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
index 928ec49..1e8e01d 100644
--- a/drivers/mmc/host/cqhci.h
+++ b/drivers/mmc/host/cqhci.h
@@ -88,6 +88,7 @@
 
 /* send status config 1 */
 #define CQHCI_SSC1			0x40
+#define CQHCI_SSC1_CBC_MASK		GENMASK(19, 16)
 
 /* send status config 2 */
 #define CQHCI_SSC2			0x44