From: Blue Swirl Date: Sat, 8 Aug 2009 20:36:08 +0000 (+0000) Subject: Sparc32: move intbit_to_level table back to slavio_intctl.c X-Git-Tag: TizenStudio_2.0_p2.3.2~208^2~11155 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=68556e2e9e7a0563027c0ea919434b37f99544d1;p=sdk%2Femulator%2Fqemu.git Sparc32: move intbit_to_level table back to slavio_intctl.c Signed-off-by: Blue Swirl --- diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c index 8eea6f9..a56feb6 100644 --- a/hw/slavio_intctl.c +++ b/hw/slavio_intctl.c @@ -67,7 +67,6 @@ typedef struct SLAVIO_INTCTLState { uint64_t irq_count[32]; #endif qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS]; - const uint32_t *intbit_to_level; uint32_t cputimer_lbit, cputimer_mbit; uint32_t cputimer_bit; uint32_t pil_out[MAX_CPUS]; @@ -252,6 +251,11 @@ void slavio_irq_info(Monitor *mon, void *opaque) #endif } +static const uint32_t intbit_to_level[] = { + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, +}; + static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs) { uint32_t pending = s->intregm_pending, pil_pending; @@ -266,7 +270,7 @@ static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs) (i == s->target_cpu)) { for (j = 0; j < 32; j++) { if (pending & (1 << j)) - pil_pending |= 1 << s->intbit_to_level[j]; + pil_pending |= 1 << intbit_to_level[j]; } } pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16; @@ -296,7 +300,7 @@ static void slavio_set_irq(void *opaque, int irq, int level) { SLAVIO_INTCTLState *s = opaque; uint32_t mask = 1 << irq; - uint32_t pil = s->intbit_to_level[irq]; + uint32_t pil = intbit_to_level[irq]; DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil, level); @@ -397,7 +401,7 @@ static void slavio_intctl_init1(SysBusDevice *dev) slavio_intctlm_mem_write, s); sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory); s->cputimer_mbit = 1 << s->cputimer_bit; - s->cputimer_lbit = 1 << s->intbit_to_level[s->cputimer_bit]; + s->cputimer_lbit = 1 << intbit_to_level[s->cputimer_bit]; for (i = 0; i < MAX_CPUS; i++) { for (j = 0; j < MAX_PILS; j++) { @@ -422,11 +426,6 @@ static SysBusDeviceInfo slavio_intctl_info = { .qdev.size = sizeof(SLAVIO_INTCTLState), .qdev.props = (Property[]) { { - .name = "intbit_to_level", - .info = &qdev_prop_ptr, - .offset = offsetof(SLAVIO_INTCTLState, intbit_to_level), - }, - { .name = "cputimer_bit", .info = &qdev_prop_uint32, .offset = offsetof(SLAVIO_INTCTLState, cputimer_bit), diff --git a/hw/sun4m.c b/hw/sun4m.c index f050b0b..54c468c 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -105,7 +105,6 @@ struct sun4m_hwdef { uint8_t nvram_machine_id; uint16_t machine_id; uint32_t iommu_version; - uint32_t intbit_to_level[32]; uint64_t max_mem; const char * const default_cpu_model; }; @@ -145,7 +144,6 @@ struct sun4c_hwdef { uint8_t nvram_machine_id; uint16_t machine_id; uint32_t iommu_version; - uint32_t intbit_to_level[32]; uint64_t max_mem; const char * const default_cpu_model; }; @@ -400,7 +398,6 @@ static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, static DeviceState *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg, - const uint32_t *intbit_to_level, qemu_irq **parent_irq, unsigned int cputimer) { @@ -409,7 +406,6 @@ static DeviceState *slavio_intctl_init(target_phys_addr_t addr, unsigned int i, j; dev = qdev_create(NULL, "slavio_intctl"); - qdev_prop_set_ptr(dev, "intbit_to_level", (void *)intbit_to_level); qdev_prop_set_uint32(dev, "cputimer_bit", cputimer); qdev_init(dev); @@ -781,7 +777,6 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, dev = slavio_intctl_init(hwdef->intctl_base, hwdef->intctl_base + 0x10000ULL, - &hwdef->intbit_to_level[0], cpu_irqs, hwdef->clock_irq); @@ -941,10 +936,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = ss5_id, .iommu_version = 0x05000000, - .intbit_to_level = { - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, - }, .max_mem = 0x10000000, .default_cpu_model = "Fujitsu MB86904", }, @@ -982,10 +973,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x72, .machine_id = ss10_id, .iommu_version = 0x03000000, - .intbit_to_level = { - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, - }, .max_mem = 0xf00000000ULL, .default_cpu_model = "TI SuperSparc II", }, @@ -1021,10 +1008,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x71, .machine_id = ss600mp_id, .iommu_version = 0x01000000, - .intbit_to_level = { - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, - }, .max_mem = 0xf00000000ULL, .default_cpu_model = "TI SuperSparc II", }, @@ -1062,10 +1045,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x72, .machine_id = ss20_id, .iommu_version = 0x13000000, - .intbit_to_level = { - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, - }, .max_mem = 0xf00000000ULL, .default_cpu_model = "TI SuperSparc II", }, @@ -1100,10 +1079,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = vger_id, .iommu_version = 0x05000000, - .intbit_to_level = { - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, - }, .max_mem = 0x10000000, .default_cpu_model = "Fujitsu MB86904", }, @@ -1137,10 +1112,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = lx_id, .iommu_version = 0x04000000, - .intbit_to_level = { - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, - }, .max_mem = 0x10000000, .default_cpu_model = "TI MicroSparc I", }, @@ -1177,10 +1148,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = ss4_id, .iommu_version = 0x05000000, - .intbit_to_level = { - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, - }, .max_mem = 0x10000000, .default_cpu_model = "Fujitsu MB86904", }, @@ -1215,10 +1182,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = scls_id, .iommu_version = 0x05000000, - .intbit_to_level = { - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, - }, .max_mem = 0x10000000, .default_cpu_model = "TI MicroSparc I", }, @@ -1253,10 +1216,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = sbook_id, .iommu_version = 0x05000000, - .intbit_to_level = { - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, - }, .max_mem = 0x10000000, .default_cpu_model = "TI MicroSparc I", },