From: Julian Brown Date: Wed, 7 Jun 2006 14:31:51 +0000 (+0000) Subject: * gas/arm/itblock.s: New file. Helper macro for making all-true IT X-Git-Tag: newlib-csl-sourcerygxx-3_4_4-25~355 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=67c6cbaef454ed07cc5f3e6b89aafde903b32e35;p=external%2Fbinutils.git * gas/arm/itblock.s: New file. Helper macro for making all-true IT blocks. * gas/arm/neon-cond-bad-inc.s: New test. Make sure unconditional Neon instructions are rejected... * gas/arm/neon-cond-bad.s: In ARM mode, and... * gas/arm/neon-cond-bad_t2.s: Accepted in Thumb mode (with IT). * gas/arm/neon-cond-bad.l: Expected error output in ARM mode. * gas/arm/neon-cond-bad.d: Control ARM mode test. * gas/arm/neon-cond-bad_t2.d: Expected output in Thumb mode. * gas/arm/vfp-neon-syntax-inc.s: Test VFP Neon-style syntax. * gas/arm/vfp-neon-syntax.s: ...in ARM mode. * gas/arm/vfp-neon-syntax_t2.s: ...and Thumb mode. * gas/arm/vfp-neon-syntax.d: Expected output in ARM mode. * gas/arm/vfp-neon-syntax_t2.d: Expected output in Thumb mode. --- diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index a526563..920353a 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,20 @@ +2006-06-07 Julian Brown + + * gas/arm/itblock.s: New file. Helper macro for making all-true IT + blocks. + * gas/arm/neon-cond-bad-inc.s: New test. Make sure unconditional + Neon instructions are rejected... + * gas/arm/neon-cond-bad.s: In ARM mode, and... + * gas/arm/neon-cond-bad_t2.s: Accepted in Thumb mode (with IT). + * gas/arm/neon-cond-bad.l: Expected error output in ARM mode. + * gas/arm/neon-cond-bad.d: Control ARM mode test. + * gas/arm/neon-cond-bad_t2.d: Expected output in Thumb mode. + * gas/arm/vfp-neon-syntax-inc.s: Test VFP Neon-style syntax. + * gas/arm/vfp-neon-syntax.s: ...in ARM mode. + * gas/arm/vfp-neon-syntax_t2.s: ...and Thumb mode. + * gas/arm/vfp-neon-syntax.d: Expected output in ARM mode. + * gas/arm/vfp-neon-syntax_t2.d: Expected output in Thumb mode. + 2006-06-06 Paul Brook * gas/arm/thumb2_bcond.d: Update expected output. diff --git a/gas/testsuite/gas/arm/itblock.s b/gas/testsuite/gas/arm/itblock.s new file mode 100644 index 0000000..0fb3c19 --- /dev/null +++ b/gas/testsuite/gas/arm/itblock.s @@ -0,0 +1,21 @@ +# All-true IT block macro. + + .macro itblock num cond="" + .if x\cond != x + .if \num == 4 + itttt \cond + .else + .if \num == 3 + ittt \cond + .else + .if \num == 2 + itt \cond + .else + .if \num == 1 + .it \cond + .endif + .endif + .endif + .endif + .endif + .endm diff --git a/gas/testsuite/gas/arm/neon-cond-bad-inc.s b/gas/testsuite/gas/arm/neon-cond-bad-inc.s new file mode 100644 index 0000000..a92d196 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad-inc.s @@ -0,0 +1,57 @@ +# Check for illegal conditional Neon instructions in ARM mode. The instructions +# which overlap with VFP are the tricky cases, so test those. + + .include "itblock.s" + + .syntax unified + .text +func: + itblock 4 eq + vmoveq q0,q1 + vmoveq d0,d1 + vmoveq.i32 q0,#0 + vmoveq.i32 d0,#0 + @ Following four *can* be conditional. + itblock 4 eq + vmoveq.32 d0[1], r2 + vmoveq d0,r1,r2 + vmoveq.32 r2,d1[0] + vmoveq r0,r1,d2 + + .macro dyadic_eq op eq="eq" f32=".f32" + itblock 2 eq + \op\eq\f32 d0,d1,d2 + \op\eq\f32 q0,q1,q2 + .endm + + dyadic_eq vmul + dyadic_eq vmla + dyadic_eq vmls + dyadic_eq vadd + dyadic_eq vsub + + .macro monadic_eq op eq="eq" f32=".f32" + itblock 2 eq + \op\eq\f32 d0,d1 + \op\eq\f32 q0,q1 + .endm + + monadic_eq vabs + monadic_eq vneg + + .macro cvt to from dot="." + itblock 2 eq + vcvteq\dot\to\dot\from d0,d1 + vcvteq\dot\to\dot\from q0,q1 + .endm + + cvt s32 f32 + cvt u32 f32 + cvt f32 s32 + cvt f32 u32 + + itblock 4 eq + vdupeq.32 d0,r1 + vdupeq.32 q0,r1 + vdupeq.32 d0,d1[0] + vdupeq.32 q0,d1[1] diff --git a/gas/testsuite/gas/arm/neon-cond-bad.d b/gas/testsuite/gas/arm/neon-cond-bad.d new file mode 100644 index 0000000..105ba4d --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad.d @@ -0,0 +1,3 @@ +# name: Illegal conditions in Neon instructions, ARM mode +# as: -mfpu=neon -I$srcdir/$subdir +# error-output: neon-cond-bad.l diff --git a/gas/testsuite/gas/arm/neon-cond-bad.l b/gas/testsuite/gas/arm/neon-cond-bad.l new file mode 100644 index 0000000..a79f79d --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad.l @@ -0,0 +1,29 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: instruction cannot be conditional -- `vmoveq q0,q1' +[^:]*:11: Error: instruction cannot be conditional -- `vmoveq d0,d1' +[^:]*:12: Error: instruction cannot be conditional -- `vmoveq\.i32 q0,#0' +[^:]*:13: Error: instruction cannot be conditional -- `vmoveq\.i32 d0,#0' +[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 d0,d1,d2' +[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 q0,q1,q2' +[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 d0,d1,d2' +[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 q0,q1,q2' +[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 d0,d1,d2' +[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 q0,q1,q2' +[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 d0,d1,d2' +[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 q0,q1,q2' +[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2' +[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 q0,q1,q2' +[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1' +[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 q0,q1' +[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1' +[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 q0,q1' +[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1' +[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 q0,q1' +[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 d0,d1' +[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 q0,q1' +[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 d0,d1' +[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 q0,q1' +[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 d0,d1' +[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 q0,q1' +[^:]*:56: Error: instruction cannot be conditional -- `vdupeq\.32 d0,d1\[0\]' +[^:]*:57: Error: instruction cannot be conditional -- `vdupeq\.32 q0,d1\[1\]' diff --git a/gas/testsuite/gas/arm/neon-cond-bad.s b/gas/testsuite/gas/arm/neon-cond-bad.s new file mode 100644 index 0000000..16afd86 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad.s @@ -0,0 +1,2 @@ + .arm + .include "neon-cond-bad-inc.s" diff --git a/gas/testsuite/gas/arm/neon-cond-bad_t2.d b/gas/testsuite/gas/arm/neon-cond-bad_t2.d new file mode 100644 index 0000000..517caa7 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad_t2.d @@ -0,0 +1,55 @@ +# name: Conditions in Neon instructions, Thumb mode (illegal in ARM). +# as: -mfpu=neon -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ef22 0152 vorreq q0, q1, q1 +0[0-9a-f]+ <[^>]+> ef21 0111 vorreq d0, d1, d1 +0[0-9a-f]+ <[^>]+> ef80 0050 vmoveq\.i32 q0, #0 ; 0x00000000 +0[0-9a-f]+ <[^>]+> ef80 0010 vmoveq\.i32 d0, #0 ; 0x00000000 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ee20 2b10 vmoveq\.32 d0\[1\], r2 +0[0-9a-f]+ <[^>]+> ec42 1b10 vmoveq d0, r1, r2 +0[0-9a-f]+ <[^>]+> ee11 2b10 vmoveq\.32 r2, d1\[0\] +0[0-9a-f]+ <[^>]+> ec51 0b12 vmoveq r0, r1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ff01 0d12 vmuleq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ff02 0d54 vmuleq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef01 0d12 vmlaeq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef02 0d54 vmlaeq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef21 0d12 vmlseq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef22 0d54 vmlseq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef01 0d02 vaddeq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef02 0d44 vaddeq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef21 0d02 vsubeq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef22 0d44 vsubeq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffb9 0701 vabseq\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffb9 0742 vabseq\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffb9 0781 vnegeq\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffb9 07c2 vnegeq\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0701 vcvteq\.s32\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 0742 vcvteq\.s32\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0781 vcvteq\.u32\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 07c2 vcvteq\.u32\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0601 vcvteq\.f32\.s32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 0642 vcvteq\.f32\.s32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0681 vcvteq\.f32\.u32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 06c2 vcvteq\.f32\.u32 q0, q1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ee80 1b10 vdupeq\.32 d0, r1 +0[0-9a-f]+ <[^>]+> eea0 1b10 vdupeq\.32 q0, r1 +0[0-9a-f]+ <[^>]+> ffb4 0c01 vdupeq\.32 d0, d1\[0\] +0[0-9a-f]+ <[^>]+> ffbc 0c41 vdupeq\.32 q0, d1\[1\] diff --git a/gas/testsuite/gas/arm/neon-cond-bad_t2.s b/gas/testsuite/gas/arm/neon-cond-bad_t2.s new file mode 100644 index 0000000..2655d11 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad_t2.s @@ -0,0 +1,2 @@ + .thumb + .include "neon-cond-bad-inc.s" diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s b/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s new file mode 100644 index 0000000..d61ae60 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s @@ -0,0 +1,162 @@ +@ VFP with Neon-style syntax + .syntax unified + + .include "itblock.s" + +func: + .macro testvmov cond="" f32=".f32" f64=".f64" + itblock 4 \cond + vmov\cond\f32 s0,s1 + vmov\cond\f64 d0,d1 + vmov\cond\f32 s0,#0.25 + vmov\cond\f64 d0,#1 + itblock 4 \cond + vmov\cond r0,s1 + vmov\cond s0,r1 + vmov\cond r0,r1,s2,s3 + vmov\cond s0,s1,r2,r4 + .endm + + @ Test VFP vmov variants. These can all be conditional. + testvmov + testvmov eq + + .macro monadic op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,s1 + \op\cond\f64 d0,d1 + .endm + + .macro monadic_c op + monadic \op + monadic \op eq + .endm + + .macro dyadic op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,s1,s2 + \op\cond\f64 d0,d1,d2 + .endm + + .macro dyadic_c op + dyadic \op + dyadic \op eq + .endm + + .macro dyadicz op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,#0 + \op\cond\f64 d0,#0 + .endm + + .macro dyadicz_c op + dyadicz \op + dyadicz \op eq + .endm + + monadic_c vsqrt + monadic_c vabs + monadic_c vneg + monadic_c vcmp + monadic_c vcmpe + + dyadic_c vnmul + dyadic_c vnmla + dyadic_c vnmls + + dyadic_c vmul + dyadic_c vmla + dyadic_c vmls + + dyadic_c vadd + dyadic_c vsub + + dyadic_c vdiv + + dyadicz_c vcmp + dyadicz_c vcmpe + + .macro cvtz cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" + itblock 4 \cond + vcvtz\cond\s32\f32 s0,s1 + vcvtz\cond\u32\f32 s0,s1 + vcvtz\cond\s32\f64 s0,d1 + vcvtz\cond\u32\f64 s0,d1 + .endm + + cvtz + cvtz eq + + .macro cvt cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" + itblock 4 \cond + vcvt\cond\s32\f32 s0,s1 + vcvt\cond\u32\f32 s0,s1 + vcvt\cond\f32\s32 s0,s1 + vcvt\cond\f32\u32 s0,s1 + itblock 4 \cond + vcvt\cond\f32\f64 s0,d1 + vcvt\cond\f64\f32 d0,s1 + vcvt\cond\s32\f64 s0,d1 + vcvt\cond\u32\f64 s0,d1 + itblock 2 \cond + vcvt\cond\f64\s32 d0,s1 + vcvt\cond\f64\u32 d0,s1 + .endm + + cvt + cvt eq + + .macro cvti cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" s16=".s16" u16=".u16" + itblock 4 \cond + vcvt\cond\s32\f32 s0,s0,#1 + vcvt\cond\u32\f32 s0,s0,#1 + vcvt\cond\f32\s32 s0,s0,#1 + vcvt\cond\f32\u32 s0,s0,#1 + itblock 4 \cond + vcvt\cond\s32\f64 d0,d0,#1 + vcvt\cond\u32\f64 d0,d0,#1 + vcvt\cond\f64\s32 d0,d0,#1 + vcvt\cond\f64\u32 d0,d0,#1 + itblock 4 \cond + vcvt\cond\f32\s16 s0,s0,#1 + vcvt\cond\f32\u16 s0,s0,#1 + vcvt\cond\f64\s16 d0,d0,#1 + vcvt\cond\f64\u16 d0,d0,#1 + itblock 4 \cond + vcvt\cond\s16\f32 s0,s0,#1 + vcvt\cond\u16\f32 s0,s0,#1 + vcvt\cond\s16\f64 d0,d0,#1 + vcvt\cond\u16\f64 d0,d0,#1 + .endm + + cvti + cvti eq + + .macro multi op cond="" n="" ia="ia" db="db" + itblock 4 \cond + \op\n\cond r0,{s3-s6} + \op\ia\cond r0,{s3-s6} + \op\ia\cond r0!,{s3-s6} + \op\db\cond r0!,{s3-s6} + itblock 4 \cond + \op\n\cond r0,{d3-d6} + \op\ia\cond r0,{d3-d6} + \op\ia\cond r0!,{d3-d6} + \op\db\cond r0!,{d3-d6} + .endm + + multi vldm + multi vldm eq + multi vstm + multi vstm eq + + .macro single op cond="" + itblock 2 \cond + \op\cond s0,[r0,#4] + \op\cond d0,[r0,#4] + .endm + + single vldr + single vldr eq + single vstr + single vstr eq diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax.d b/gas/testsuite/gas/arm/vfp-neon-syntax.d new file mode 100644 index 0000000..8b6c079 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax.d @@ -0,0 +1,187 @@ +# name: VFP Neon-style syntax, ARM mode +# as: -mfpu=vfp3 -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> eeb00a60 fcpys s0, s1 +0[0-9a-f]+ <[^>]+> eeb00b41 fcpyd d0, d1 +0[0-9a-f]+ <[^>]+> eeb00a05 fconsts s0, #80 +0[0-9a-f]+ <[^>]+> eeb00b07 fconstd d0, #112 +0[0-9a-f]+ <[^>]+> ee100a90 fmrs r0, s1 +0[0-9a-f]+ <[^>]+> ee001a10 fmsr s0, r1 +0[0-9a-f]+ <[^>]+> ec510a11 fmrrs r0, r1, {s2, s3} +0[0-9a-f]+ <[^>]+> ec442a10 fmsrr r2, r4, {s0, s1} +0[0-9a-f]+ <[^>]+> 0eb00a60 fcpyseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb00b41 fcpydeq d0, d1 +0[0-9a-f]+ <[^>]+> 0eb00a05 fconstseq s0, #80 +0[0-9a-f]+ <[^>]+> 0eb00b07 fconstdeq d0, #112 +0[0-9a-f]+ <[^>]+> 0e100a90 fmrseq r0, s1 +0[0-9a-f]+ <[^>]+> 0e001a10 fmsreq s0, r1 +0[0-9a-f]+ <[^>]+> 0c510a11 fmrrseq r0, r1, {s2, s3} +0[0-9a-f]+ <[^>]+> 0c442a10 fmsrreq r2, r4, {s0, s1} +0[0-9a-f]+ <[^>]+> eeb10ae0 fsqrts s0, s1 +0[0-9a-f]+ <[^>]+> eeb10bc1 fsqrtd d0, d1 +0[0-9a-f]+ <[^>]+> 0eb10ae0 fsqrtseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb10bc1 fsqrtdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb00ae0 fabss s0, s1 +0[0-9a-f]+ <[^>]+> eeb00bc1 fabsd d0, d1 +0[0-9a-f]+ <[^>]+> 0eb00ae0 fabsseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb00bc1 fabsdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb10a60 fnegs s0, s1 +0[0-9a-f]+ <[^>]+> eeb10b41 fnegd d0, d1 +0[0-9a-f]+ <[^>]+> 0eb10a60 fnegseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb10b41 fnegdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb40a60 fcmps s0, s1 +0[0-9a-f]+ <[^>]+> eeb40b41 fcmpd d0, d1 +0[0-9a-f]+ <[^>]+> 0eb40a60 fcmpseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb40b41 fcmpdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb40ae0 fcmpes s0, s1 +0[0-9a-f]+ <[^>]+> eeb40bc1 fcmped d0, d1 +0[0-9a-f]+ <[^>]+> 0eb40ae0 fcmpeseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb40bc1 fcmpedeq d0, d1 +0[0-9a-f]+ <[^>]+> ee200ac1 fnmuls s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee210b42 fnmuld d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e200ac1 fnmulseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e210b42 fnmuldeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee000ac1 fnmacs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee010b42 fnmacd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e000ac1 fnmacseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e010b42 fnmacdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee100ac1 fnmscs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee110b42 fnmscd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e100ac1 fnmscseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e110b42 fnmscdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee200a81 fmuls s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee210b02 fmuld d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e200a81 fmulseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e210b02 fmuldeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee000a81 fmacs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee010b02 fmacd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e000a81 fmacseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e010b02 fmacdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee100a81 fmscs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee110b02 fmscd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e100a81 fmscseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e110b02 fmscdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee300a81 fadds s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee310b02 faddd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e300a81 faddseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e310b02 fadddeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee300ac1 fsubs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee310b42 fsubd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e300ac1 fsubseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e310b42 fsubdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee800a81 fdivs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee810b02 fdivd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e800a81 fdivseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e810b02 fdivdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> eeb50a40 fcmpzs s0 +0[0-9a-f]+ <[^>]+> eeb50b40 fcmpzd d0 +0[0-9a-f]+ <[^>]+> 0eb50a40 fcmpzseq s0 +0[0-9a-f]+ <[^>]+> 0eb50b40 fcmpzdeq d0 +0[0-9a-f]+ <[^>]+> eeb50ac0 fcmpezs s0 +0[0-9a-f]+ <[^>]+> eeb50bc0 fcmpezd d0 +0[0-9a-f]+ <[^>]+> 0eb50ac0 fcmpezseq s0 +0[0-9a-f]+ <[^>]+> 0eb50bc0 fcmpezdeq d0 +0[0-9a-f]+ <[^>]+> eebd0ae0 ftosizs s0, s1 +0[0-9a-f]+ <[^>]+> eebc0ae0 ftouizs s0, s1 +0[0-9a-f]+ <[^>]+> eebd0bc1 ftosizd s0, d1 +0[0-9a-f]+ <[^>]+> eebc0bc1 ftouizd s0, d1 +0[0-9a-f]+ <[^>]+> 0ebd0ae0 ftosizseq s0, s1 +0[0-9a-f]+ <[^>]+> 0ebc0ae0 ftouizseq s0, s1 +0[0-9a-f]+ <[^>]+> 0ebd0bc1 ftosizdeq s0, d1 +0[0-9a-f]+ <[^>]+> 0ebc0bc1 ftouizdeq s0, d1 +0[0-9a-f]+ <[^>]+> eebd0a60 ftosis s0, s1 +0[0-9a-f]+ <[^>]+> eebc0a60 ftouis s0, s1 +0[0-9a-f]+ <[^>]+> eeb80ae0 fsitos s0, s1 +0[0-9a-f]+ <[^>]+> eeb80a60 fuitos s0, s1 +0[0-9a-f]+ <[^>]+> eeb70bc1 fcvtsd s0, d1 +0[0-9a-f]+ <[^>]+> eeb70ae0 fcvtds d0, s1 +0[0-9a-f]+ <[^>]+> eebd0b41 ftosid s0, d1 +0[0-9a-f]+ <[^>]+> eebc0b41 ftouid s0, d1 +0[0-9a-f]+ <[^>]+> eeb80be0 fsitod d0, s1 +0[0-9a-f]+ <[^>]+> eeb80b60 fuitod d0, s1 +0[0-9a-f]+ <[^>]+> 0ebd0a60 ftosiseq s0, s1 +0[0-9a-f]+ <[^>]+> 0ebc0a60 ftouiseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb80ae0 fsitoseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb80a60 fuitoseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb70bc1 fcvtsdeq s0, d1 +0[0-9a-f]+ <[^>]+> 0eb70ae0 fcvtdseq d0, s1 +0[0-9a-f]+ <[^>]+> 0ebd0b41 ftosideq s0, d1 +0[0-9a-f]+ <[^>]+> 0ebc0b41 ftouideq s0, d1 +0[0-9a-f]+ <[^>]+> 0eb80be0 fsitodeq d0, s1 +0[0-9a-f]+ <[^>]+> 0eb80b60 fuitodeq d0, s1 +0[0-9a-f]+ <[^>]+> eebe0aef ftosls s0, #1 +0[0-9a-f]+ <[^>]+> eebf0aef ftouls s0, #1 +0[0-9a-f]+ <[^>]+> eeba0aef fsltos s0, #1 +0[0-9a-f]+ <[^>]+> eebb0aef fultos s0, #1 +0[0-9a-f]+ <[^>]+> eebe0bef ftosld d0, #1 +0[0-9a-f]+ <[^>]+> eebf0bef ftould d0, #1 +0[0-9a-f]+ <[^>]+> eeba0bef fsltod d0, #1 +0[0-9a-f]+ <[^>]+> eebb0bef fultod d0, #1 +0[0-9a-f]+ <[^>]+> eeba0a67 fshtos s0, #1 +0[0-9a-f]+ <[^>]+> eebb0a67 fuhtos s0, #1 +0[0-9a-f]+ <[^>]+> eeba0b67 fshtod d0, #1 +0[0-9a-f]+ <[^>]+> eebb0b67 fuhtod d0, #1 +0[0-9a-f]+ <[^>]+> eebe0a67 ftoshs s0, #1 +0[0-9a-f]+ <[^>]+> eebf0a67 ftouhs s0, #1 +0[0-9a-f]+ <[^>]+> eebe0b67 ftoshd d0, #1 +0[0-9a-f]+ <[^>]+> eebf0b67 ftouhd d0, #1 +0[0-9a-f]+ <[^>]+> 0ebe0aef ftoslseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebf0aef ftoulseq s0, #1 +0[0-9a-f]+ <[^>]+> 0eba0aef fsltoseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebb0aef fultoseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebe0bef ftosldeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebf0bef ftouldeq d0, #1 +0[0-9a-f]+ <[^>]+> 0eba0bef fsltodeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebb0bef fultodeq d0, #1 +0[0-9a-f]+ <[^>]+> 0eba0a67 fshtoseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebb0a67 fuhtoseq s0, #1 +0[0-9a-f]+ <[^>]+> 0eba0b67 fshtodeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebb0b67 fuhtodeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebe0a67 ftoshseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebf0a67 ftouhseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebe0b67 ftoshdeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebf0b67 ftouhdeq d0, #1 +0[0-9a-f]+ <[^>]+> ecd01a04 fldmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecd01a04 fldmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecf01a04 fldmias r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed701a04 fldmdbs r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec903b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec903b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ecb03b08 vldmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed303b08 vldmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0cd01a04 fldmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0cd01a04 fldmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0cf01a04 fldmiaseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0d701a04 fldmdbseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0c903b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0c903b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0cb03b08 vldmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0d303b08 vldmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ecc01a04 fstmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecc01a04 fstmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ece01a04 fstmias r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed601a04 fstmdbs r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec803b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec803b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> eca03b08 vstmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed203b08 vstmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0cc01a04 fstmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0cc01a04 fstmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0ce01a04 fstmiaseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0d601a04 fstmdbseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0c803b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0c803b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0ca03b08 vstmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0d203b08 vstmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed900a01 flds s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed900b01 vldr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d900a01 fldseq s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d900b01 vldreq d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed800a01 fsts s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed800b01 vstr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d800a01 fstseq s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d800b01 vstreq d0, \[r0, #4\] diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax.s b/gas/testsuite/gas/arm/vfp-neon-syntax.s new file mode 100644 index 0000000..7c0bc63 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax.s @@ -0,0 +1,2 @@ + .arm + .include "vfp-neon-syntax-inc.s" diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d new file mode 100644 index 0000000..fa73b03 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d @@ -0,0 +1,219 @@ +# name: VFP Neon-style syntax, Thumb mode +# as: -mfpu=vfp3 -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> eeb0 0a60 fcpys s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0b41 fcpyd d0, d1 +0[0-9a-f]+ <[^>]+> eeb0 0a05 fconsts s0, #80 +0[0-9a-f]+ <[^>]+> eeb0 0b07 fconstd d0, #112 +0[0-9a-f]+ <[^>]+> ee10 0a90 fmrs r0, s1 +0[0-9a-f]+ <[^>]+> ee00 1a10 fmsr s0, r1 +0[0-9a-f]+ <[^>]+> ec51 0a11 fmrrs r0, r1, {s2, s3} +0[0-9a-f]+ <[^>]+> ec44 2a10 fmsrr r2, r4, {s0, s1} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eeb0 0a60 fcpyseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0b41 fcpydeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb0 0a05 fconstseq s0, #80 +0[0-9a-f]+ <[^>]+> eeb0 0b07 fconstdeq d0, #112 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ee10 0a90 fmrseq r0, s1 +0[0-9a-f]+ <[^>]+> ee00 1a10 fmsreq s0, r1 +0[0-9a-f]+ <[^>]+> ec51 0a11 fmrrseq r0, r1, {s2, s3} +0[0-9a-f]+ <[^>]+> ec44 2a10 fmsrreq r2, r4, {s0, s1} +0[0-9a-f]+ <[^>]+> eeb1 0ae0 fsqrts s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0bc1 fsqrtd d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb1 0ae0 fsqrtseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0bc1 fsqrtdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb0 0ae0 fabss s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0bc1 fabsd d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb0 0ae0 fabsseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0bc1 fabsdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb1 0a60 fnegs s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0b41 fnegd d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb1 0a60 fnegseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0b41 fnegdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb4 0a60 fcmps s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0b41 fcmpd d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb4 0a60 fcmpseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0b41 fcmpdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb4 0ae0 fcmpes s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0bc1 fcmped d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb4 0ae0 fcmpeseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0bc1 fcmpedeq d0, d1 +0[0-9a-f]+ <[^>]+> ee20 0ac1 fnmuls s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b42 fnmuld d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee20 0ac1 fnmulseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b42 fnmuldeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee00 0ac1 fnmacs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b42 fnmacd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee00 0ac1 fnmacseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b42 fnmacdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee10 0ac1 fnmscs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b42 fnmscd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee10 0ac1 fnmscseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b42 fnmscdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee20 0a81 fmuls s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b02 fmuld d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee20 0a81 fmulseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b02 fmuldeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee00 0a81 fmacs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b02 fmacd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee00 0a81 fmacseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b02 fmacdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee10 0a81 fmscs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b02 fmscd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee10 0a81 fmscseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b02 fmscdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee30 0a81 fadds s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b02 faddd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee30 0a81 faddseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b02 fadddeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee30 0ac1 fsubs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b42 fsubd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee30 0ac1 fsubseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b42 fsubdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee80 0a81 fdivs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee81 0b02 fdivd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee80 0a81 fdivseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee81 0b02 fdivdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> eeb5 0a40 fcmpzs s0 +0[0-9a-f]+ <[^>]+> eeb5 0b40 fcmpzd d0 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb5 0a40 fcmpzseq s0 +0[0-9a-f]+ <[^>]+> eeb5 0b40 fcmpzdeq d0 +0[0-9a-f]+ <[^>]+> eeb5 0ac0 fcmpezs s0 +0[0-9a-f]+ <[^>]+> eeb5 0bc0 fcmpezd d0 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb5 0ac0 fcmpezseq s0 +0[0-9a-f]+ <[^>]+> eeb5 0bc0 fcmpezdeq d0 +0[0-9a-f]+ <[^>]+> eebd 0ae0 ftosizs s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0ae0 ftouizs s0, s1 +0[0-9a-f]+ <[^>]+> eebd 0bc1 ftosizd s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0bc1 ftouizd s0, d1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebd 0ae0 ftosizseq s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0ae0 ftouizseq s0, s1 +0[0-9a-f]+ <[^>]+> eebd 0bc1 ftosizdeq s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0bc1 ftouizdeq s0, d1 +0[0-9a-f]+ <[^>]+> eebd 0a60 ftosis s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0a60 ftouis s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0ae0 fsitos s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0a60 fuitos s0, s1 +0[0-9a-f]+ <[^>]+> eeb7 0bc1 fcvtsd s0, d1 +0[0-9a-f]+ <[^>]+> eeb7 0ae0 fcvtds d0, s1 +0[0-9a-f]+ <[^>]+> eebd 0b41 ftosid s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0b41 ftouid s0, d1 +0[0-9a-f]+ <[^>]+> eeb8 0be0 fsitod d0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0b60 fuitod d0, s1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebd 0a60 ftosiseq s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0a60 ftouiseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0ae0 fsitoseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0a60 fuitoseq s0, s1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eeb7 0bc1 fcvtsdeq s0, d1 +0[0-9a-f]+ <[^>]+> eeb7 0ae0 fcvtdseq d0, s1 +0[0-9a-f]+ <[^>]+> eebd 0b41 ftosideq s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0b41 ftouideq s0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb8 0be0 fsitodeq d0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0b60 fuitodeq d0, s1 +0[0-9a-f]+ <[^>]+> eebe 0aef ftosls s0, #1 +0[0-9a-f]+ <[^>]+> eebf 0aef ftouls s0, #1 +0[0-9a-f]+ <[^>]+> eeba 0aef fsltos s0, #1 +0[0-9a-f]+ <[^>]+> eebb 0aef fultos s0, #1 +0[0-9a-f]+ <[^>]+> eebe 0bef ftosld d0, #1 +0[0-9a-f]+ <[^>]+> eebf 0bef ftould d0, #1 +0[0-9a-f]+ <[^>]+> eeba 0bef fsltod d0, #1 +0[0-9a-f]+ <[^>]+> eebb 0bef fultod d0, #1 +0[0-9a-f]+ <[^>]+> eeba 0a67 fshtos s0, #1 +0[0-9a-f]+ <[^>]+> eebb 0a67 fuhtos s0, #1 +0[0-9a-f]+ <[^>]+> eeba 0b67 fshtod d0, #1 +0[0-9a-f]+ <[^>]+> eebb 0b67 fuhtod d0, #1 +0[0-9a-f]+ <[^>]+> eebe 0a67 ftoshs s0, #1 +0[0-9a-f]+ <[^>]+> eebf 0a67 ftouhs s0, #1 +0[0-9a-f]+ <[^>]+> eebe 0b67 ftoshd d0, #1 +0[0-9a-f]+ <[^>]+> eebf 0b67 ftouhd d0, #1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebe 0aef ftoslseq s0, #1 +0[0-9a-f]+ <[^>]+> eebf 0aef ftoulseq s0, #1 +0[0-9a-f]+ <[^>]+> eeba 0aef fsltoseq s0, #1 +0[0-9a-f]+ <[^>]+> eebb 0aef fultoseq s0, #1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebe 0bef ftosldeq d0, #1 +0[0-9a-f]+ <[^>]+> eebf 0bef ftouldeq d0, #1 +0[0-9a-f]+ <[^>]+> eeba 0bef fsltodeq d0, #1 +0[0-9a-f]+ <[^>]+> eebb 0bef fultodeq d0, #1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eeba 0a67 fshtoseq s0, #1 +0[0-9a-f]+ <[^>]+> eebb 0a67 fuhtoseq s0, #1 +0[0-9a-f]+ <[^>]+> eeba 0b67 fshtodeq d0, #1 +0[0-9a-f]+ <[^>]+> eebb 0b67 fuhtodeq d0, #1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebe 0a67 ftoshseq s0, #1 +0[0-9a-f]+ <[^>]+> eebf 0a67 ftouhseq s0, #1 +0[0-9a-f]+ <[^>]+> eebe 0b67 ftoshdeq d0, #1 +0[0-9a-f]+ <[^>]+> eebf 0b67 ftouhdeq d0, #1 +0[0-9a-f]+ <[^>]+> ecd0 1a04 fldmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecd0 1a04 fldmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecf0 1a04 fldmias r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed70 1a04 fldmdbs r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ecb0 3b08 vldmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed30 3b08 vldmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ecd0 1a04 fldmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecd0 1a04 fldmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecf0 1a04 fldmiaseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed70 1a04 fldmdbseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ecb0 3b08 vldmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed30 3b08 vldmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ecc0 1a04 fstmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecc0 1a04 fstmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ece0 1a04 fstmias r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed60 1a04 fstmdbs r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> eca0 3b08 vstmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed20 3b08 vstmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ecc0 1a04 fstmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecc0 1a04 fstmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ece0 1a04 fstmiaseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed60 1a04 fstmdbseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> eca0 3b08 vstmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed20 3b08 vstmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed90 0a01 flds s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed90 0b01 vldr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ed90 0a01 fldseq s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed90 0b01 vldreq d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed80 0a01 fsts s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed80 0b01 vstr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ed80 0a01 fstseq s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed80 0b01 vstreq d0, \[r0, #4\] diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s new file mode 100644 index 0000000..00f78d0 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s @@ -0,0 +1,2 @@ + .thumb + .include "vfp-neon-syntax-inc.s"