From: Mehdi Amini Date: Mon, 7 Mar 2022 10:12:43 +0000 (+0000) Subject: Apply clang-tidy fixes for modernize-use-default-member-init to MLIR (NFC) X-Git-Tag: upstream/15.0.7~14446 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=671e30a12f8c6efc0181741d7060e5f1fc88c4f2;p=platform%2Fupstream%2Fllvm.git Apply clang-tidy fixes for modernize-use-default-member-init to MLIR (NFC) --- diff --git a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp index 5c1bce7..9b74315 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp @@ -1355,8 +1355,8 @@ namespace { struct Conv1DNwcGenerator : public StructuredGenerator { Conv1DNwcGenerator(OpBuilder &builder, LinalgOp linalgOp, int strideW, int dilationW) - : StructuredGenerator(builder, linalgOp), valid(false), - strideW(strideW), dilationW(dilationW) { + : StructuredGenerator(builder, linalgOp), strideW(strideW), + dilationW(dilationW) { // Determine whether `linalgOp` can be generated with this generator if (linalgOp.getNumInputs() != 2 || linalgOp.getNumOutputs() != 1) return; @@ -1665,7 +1665,7 @@ struct Conv1DNwcGenerator : public StructuredGenerator { } private: - bool valid; + bool valid = false; int strideW, dilationW; Value lhsShaped, rhsShaped, resShaped; ShapedType lhsShapedType, rhsShapedType, resShapedType; diff --git a/mlir/lib/Dialect/Linalg/Utils/Utils.cpp b/mlir/lib/Dialect/Linalg/Utils/Utils.cpp index 3513804..431c1eb 100644 --- a/mlir/lib/Dialect/Linalg/Utils/Utils.cpp +++ b/mlir/lib/Dialect/Linalg/Utils/Utils.cpp @@ -57,7 +57,7 @@ namespace { // `d0 + 2 * d1 + d3` is tiled by [0, 0, 0, 2] but not by [0, 0, 2, 0] // struct TileCheck : public AffineExprVisitor { - TileCheck(ValueRange tileSizes) : isTiled(false), tileSizes(tileSizes) {} + TileCheck(ValueRange tileSizes) : tileSizes(tileSizes) {} void visitDimExpr(AffineDimExpr expr) { isTiled |= !isZero(tileSizes[expr.getPosition()]); @@ -69,7 +69,7 @@ struct TileCheck : public AffineExprVisitor { assert(expr.getRHS().cast().getValue() > 0 && "nonpositive multiplying coefficient"); } - bool isTiled; + bool isTiled = false; ValueRange tileSizes; }; diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp index e7a0c2d..6945e54 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp @@ -52,10 +52,9 @@ struct CodeGen { indices(numTensors, std::vector(numLoops)), highs(numTensors, std::vector(numLoops)), pidxs(numTensors, std::vector(numLoops)), - idxs(numTensors, std::vector(numLoops)), redExp(-1u), redVal(), - redKind(kNoReduc), sparseOut(op), outerParNest(nest), lexIdx(), - expValues(), expFilled(), expAdded(), expCount(), curVecLength(1), - curVecMask() {} + idxs(numTensors, std::vector(numLoops)), redVal(), sparseOut(op), + outerParNest(nest), lexIdx(), expValues(), expFilled(), expAdded(), + expCount(), curVecMask() {} /// Sparsification options. SparsificationOptions options; /// Universal dense indices and upper bounds (by index). The loops array @@ -77,9 +76,9 @@ struct CodeGen { std::vector> idxs; /// Current reduction, updated during code generation. When indices of a /// reduction are exhausted, all inner loops can use a scalarized reduction. - unsigned redExp; + unsigned redExp = -1u; Value redVal; - Reduction redKind; + Reduction redKind = kNoReduc; // Sparse tensor as output. Implemented either through direct injective // insertion in lexicographic index order (where indices are updated // in the temporary array `lexIdx`) or through access pattern expansion @@ -92,7 +91,7 @@ struct CodeGen { Value expAdded; Value expCount; // Current vector length and mask. - unsigned curVecLength; + unsigned curVecLength = 1; Value curVecMask; }; diff --git a/mlir/lib/IR/Diagnostics.cpp b/mlir/lib/IR/Diagnostics.cpp index d9459ee..ea0ff5a 100644 --- a/mlir/lib/IR/Diagnostics.cpp +++ b/mlir/lib/IR/Diagnostics.cpp @@ -844,7 +844,7 @@ struct ParallelDiagnosticHandlerImpl : public llvm::PrettyStackTraceEntry { Diagnostic diag; }; - ParallelDiagnosticHandlerImpl(MLIRContext *ctx) : handlerID(0), context(ctx) { + ParallelDiagnosticHandlerImpl(MLIRContext *ctx) : context(ctx) { handlerID = ctx->getDiagEngine().registerHandler([this](Diagnostic &diag) { uint64_t tid = llvm::get_threadid(); llvm::sys::SmartScopedLock lock(mutex); @@ -942,7 +942,7 @@ struct ParallelDiagnosticHandlerImpl : public llvm::PrettyStackTraceEntry { mutable std::vector diagnostics; /// The unique id for the parallel handler. - DiagnosticEngine::HandlerID handlerID; + DiagnosticEngine::HandlerID handlerID = 0; /// The context to emit the diagnostics to. MLIRContext *context; diff --git a/mlir/lib/Parser/AffineParser.cpp b/mlir/lib/Parser/AffineParser.cpp index 7d2dd69..57a2fc2 100644 --- a/mlir/lib/Parser/AffineParser.cpp +++ b/mlir/lib/Parser/AffineParser.cpp @@ -48,7 +48,7 @@ public: AffineParser(ParserState &state, bool allowParsingSSAIds = false, function_ref parseElement = nullptr) : Parser(state), allowParsingSSAIds(allowParsingSSAIds), - parseElement(parseElement), numDimOperands(0), numSymbolOperands(0) {} + parseElement(parseElement) {} AffineMap parseAffineMapRange(unsigned numDims, unsigned numSymbols); ParseResult parseAffineMapOrIntegerSetInline(AffineMap &map, IntegerSet &set); @@ -92,8 +92,8 @@ private: private: bool allowParsingSSAIds; function_ref parseElement; - unsigned numDimOperands; - unsigned numSymbolOperands; + unsigned numDimOperands = 0; + unsigned numSymbolOperands = 0; SmallVector, 4> dimsAndSymbols; }; } // namespace diff --git a/mlir/lib/Pass/PassRegistry.cpp b/mlir/lib/Pass/PassRegistry.cpp index 5e23b9c..b47f538 100644 --- a/mlir/lib/Pass/PassRegistry.cpp +++ b/mlir/lib/Pass/PassRegistry.cpp @@ -326,11 +326,11 @@ private: /// the name is the name of a pass, the InnerPipeline is empty, since passes /// cannot contain inner pipelines. struct PipelineElement { - PipelineElement(StringRef name) : name(name), registryEntry(nullptr) {} + PipelineElement(StringRef name) : name(name) {} StringRef name; StringRef options; - const PassRegistryEntry *registryEntry; + const PassRegistryEntry *registryEntry = nullptr; std::vector innerPipeline; }; diff --git a/mlir/lib/Tools/PDLL/Parser/Parser.cpp b/mlir/lib/Tools/PDLL/Parser/Parser.cpp index 3da7783..167aee2 100644 --- a/mlir/lib/Tools/PDLL/Parser/Parser.cpp +++ b/mlir/lib/Tools/PDLL/Parser/Parser.cpp @@ -43,8 +43,7 @@ class Parser { public: Parser(ast::Context &ctx, llvm::SourceMgr &sourceMgr) : ctx(ctx), lexer(sourceMgr, ctx.getDiagEngine()), - curToken(lexer.lexToken()), curDeclScope(nullptr), - valueTy(ast::ValueType::get(ctx)), + curToken(lexer.lexToken()), valueTy(ast::ValueType::get(ctx)), valueRangeTy(ast::ValueRangeType::get(ctx)), typeTy(ast::TypeType::get(ctx)), typeRangeTy(ast::TypeRangeType::get(ctx)), @@ -469,7 +468,7 @@ private: Token curToken; /// The most recently defined decl scope. - ast::DeclScope *curDeclScope; + ast::DeclScope *curDeclScope = nullptr; llvm::SpecificBumpPtrAllocator scopeAllocator; /// The current context of the parser. diff --git a/mlir/lib/Tools/mlir-lsp-server/MLIRServer.cpp b/mlir/lib/Tools/mlir-lsp-server/MLIRServer.cpp index 97cb5f1..c13df34 100644 --- a/mlir/lib/Tools/mlir-lsp-server/MLIRServer.cpp +++ b/mlir/lib/Tools/mlir-lsp-server/MLIRServer.cpp @@ -716,7 +716,7 @@ private: int64_t version; /// The number of lines in the file. - int64_t totalNumLines; + int64_t totalNumLines = 0; /// The chunks of this file. The order of these chunks is the order in which /// they appear in the text file. @@ -728,7 +728,7 @@ MLIRTextFile::MLIRTextFile(const lsp::URIForFile &uri, StringRef fileContents, int64_t version, DialectRegistry ®istry, std::vector &diagnostics) : context(registry, MLIRContext::Threading::DISABLED), - contents(fileContents.str()), version(version), totalNumLines(0) { + contents(fileContents.str()), version(version) { context.allowUnregisteredDialects(); // Split the file into separate MLIR documents. diff --git a/mlir/lib/Transforms/CSE.cpp b/mlir/lib/Transforms/CSE.cpp index 235abda..0570c91 100644 --- a/mlir/lib/Transforms/CSE.cpp +++ b/mlir/lib/Transforms/CSE.cpp @@ -63,8 +63,7 @@ struct CSE : public CSEBase { /// Represents a single entry in the depth first traversal of a CFG. struct CFGStackNode { CFGStackNode(ScopedMapTy &knownValues, DominanceInfoNode *node) - : scope(knownValues), node(node), childIterator(node->begin()), - processed(false) {} + : scope(knownValues), node(node), childIterator(node->begin()) {} /// Scope for the known values. ScopedMapTy::ScopeTy scope; @@ -73,7 +72,7 @@ struct CSE : public CSEBase { DominanceInfoNode::const_iterator childIterator; /// If this node has been fully processed yet or not. - bool processed; + bool processed = false; }; /// Attempt to eliminate a redundant operation. Returns success if the diff --git a/mlir/lib/Transforms/Utils/ControlFlowSinkUtils.cpp b/mlir/lib/Transforms/Utils/ControlFlowSinkUtils.cpp index 0101f90..34668fa 100644 --- a/mlir/lib/Transforms/Utils/ControlFlowSinkUtils.cpp +++ b/mlir/lib/Transforms/Utils/ControlFlowSinkUtils.cpp @@ -35,8 +35,7 @@ public: /// Create an operation sinker with given dominance info. Sinker(function_ref shouldMoveIntoRegion, DominanceInfo &domInfo) - : shouldMoveIntoRegion(shouldMoveIntoRegion), domInfo(domInfo), - numSunk(0) {} + : shouldMoveIntoRegion(shouldMoveIntoRegion), domInfo(domInfo) {} /// Given a list of regions, find operations to sink and sink them. Return the /// number of operations sunk. @@ -65,7 +64,7 @@ private: /// Dominance info to determine op user dominance with respect to regions. DominanceInfo &domInfo; /// The number of operations sunk. - size_t numSunk; + size_t numSunk = 0; }; } // end anonymous namespace diff --git a/mlir/tools/mlir-tblgen/OpFormatGen.cpp b/mlir/tools/mlir-tblgen/OpFormatGen.cpp index 37e6288..c1a2007 100644 --- a/mlir/tools/mlir-tblgen/OpFormatGen.cpp +++ b/mlir/tools/mlir-tblgen/OpFormatGen.cpp @@ -301,8 +301,8 @@ struct OperationFormat { }; OperationFormat(const Operator &op) - : allOperands(false), allOperandTypes(false), allResultTypes(false), - infersResultTypes(false) { + + { operandTypes.resize(op.getNumOperands(), TypeResolution()); resultTypes.resize(op.getNumResults(), TypeResolution()); @@ -346,10 +346,10 @@ struct OperationFormat { /// A flag indicating if all operand/result types were seen. If the format /// contains these, it can not contain individual type resolvers. - bool allOperands, allOperandTypes, allResultTypes; + bool allOperands = false, allOperandTypes = false, allResultTypes = false; /// A flag indicating if this operation infers its result types - bool infersResultTypes; + bool infersResultTypes = false; /// A flag indicating if this operation has the SingleBlockImplicitTerminator /// trait. diff --git a/mlir/tools/mlir-tblgen/RewriterGen.cpp b/mlir/tools/mlir-tblgen/RewriterGen.cpp index 9310810..0159328 100644 --- a/mlir/tools/mlir-tblgen/RewriterGen.cpp +++ b/mlir/tools/mlir-tblgen/RewriterGen.cpp @@ -243,7 +243,7 @@ private: StaticMatcherHelper &staticMatcherHelper; // The next unused ID for newly created values. - unsigned nextValueId; + unsigned nextValueId = 0; raw_indented_ostream os; @@ -333,8 +333,7 @@ private: PatternEmitter::PatternEmitter(Record *pat, RecordOperatorMap *mapper, raw_ostream &os, StaticMatcherHelper &helper) : loc(pat->getLoc()), opMap(mapper), pattern(pat, mapper), - symbolInfoMap(pat->getLoc()), staticMatcherHelper(helper), nextValueId(0), - os(os) { + symbolInfoMap(pat->getLoc()), staticMatcherHelper(helper), os(os) { fmtCtx.withBuilder("rewriter"); }