From: Chandler Carruth <chandlerc@gmail.com>
Date: Tue, 24 Jul 2018 00:35:36 +0000 (+0000)
Subject: [x86/SLH] Simplify the code for hardening a loaded value. NFC.
X-Git-Tag: llvmorg-7.0.0-rc1~757
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=66fbbbca602853c4c7a8d23556f393acf6c69e7b;p=platform%2Fupstream%2Fllvm.git

[x86/SLH] Simplify the code for hardening a loaded value. NFC.

This is in preparation for extracting this into a re-usable utility in
this code.

llvm-svn: 337785
---

diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
index 93dcf95bebdc..c2453cef496b 100644
--- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
+++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
@@ -1884,35 +1884,30 @@ void X86SpeculativeLoadHardeningPass::hardenPostLoad(MachineInstr &MI) {
   auto *DefRC = MRI->getRegClass(OldDefReg);
   int DefRegBytes = TRI->getRegSizeInBits(*DefRC) / 8;
 
-  unsigned OrOpCodes[] = {X86::OR8rr, X86::OR16rr, X86::OR32rr, X86::OR64rr};
-  unsigned OrOpCode = OrOpCodes[Log2_32(DefRegBytes)];
-
-  unsigned SubRegImms[] = {X86::sub_8bit, X86::sub_16bit, X86::sub_32bit};
-
-  auto GetStateRegInRC = [&](const TargetRegisterClass &RC) {
-    unsigned StateReg = PS->SSA.GetValueAtEndOfBlock(&MBB);
+  unsigned StateReg = PS->SSA.GetValueAtEndOfBlock(&MBB);
 
-    int Bytes = TRI->getRegSizeInBits(RC) / 8;
-    // FIXME: Need to teach this about 32-bit mode.
-    if (Bytes != 8) {
-      unsigned SubRegImm = SubRegImms[Log2_32(Bytes)];
-      unsigned NarrowStateReg = MRI->createVirtualRegister(&RC);
-      BuildMI(MBB, MI.getIterator(), Loc, TII->get(TargetOpcode::COPY),
-              NarrowStateReg)
-          .addReg(StateReg, 0, SubRegImm);
-      StateReg = NarrowStateReg;
-    }
-    return StateReg;
-  };
+  // FIXME: Need to teach this about 32-bit mode.
+  if (DefRegBytes != 8) {
+    unsigned SubRegImms[] = {X86::sub_8bit, X86::sub_16bit, X86::sub_32bit};
+    unsigned SubRegImm = SubRegImms[Log2_32(DefRegBytes)];
+    unsigned NarrowStateReg = MRI->createVirtualRegister(DefRC);
+    BuildMI(MBB, MI.getIterator(), Loc, TII->get(TargetOpcode::COPY),
+            NarrowStateReg)
+        .addReg(StateReg, 0, SubRegImm);
+    StateReg = NarrowStateReg;
+  }
 
   auto InsertPt = std::next(MI.getIterator());
+
   unsigned FlagsReg = 0;
   if (isEFLAGSLive(MBB, InsertPt, *TRI))
     FlagsReg = saveEFLAGS(MBB, InsertPt, Loc);
 
-  unsigned StateReg = GetStateRegInRC(*DefRC);
   unsigned NewDefReg = MRI->createVirtualRegister(DefRC);
   DefOp.setReg(NewDefReg);
+
+  unsigned OrOpCodes[] = {X86::OR8rr, X86::OR16rr, X86::OR32rr, X86::OR64rr};
+  unsigned OrOpCode = OrOpCodes[Log2_32(DefRegBytes)];
   auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOpCode), OldDefReg)
                  .addReg(StateReg)
                  .addReg(NewDefReg);