From: Jan Kiszka <jan.kiszka@siemens.com>
Date: Wed, 29 Feb 2012 14:33:48 +0000 (+0100)
Subject: pcnet: Clear ERR in CSR0 on stop
X-Git-Tag: TizenStudio_2.0_p2.3.2~208^2~4233^2~3
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6655124ddd6442b19a4b43b27e7d5a3846c4e6a8;p=sdk%2Femulator%2Fqemu.git

pcnet: Clear ERR in CSR0 on stop

pcnet_stop already clears any reason (BABL, CERR, MISS, MERR) why ERR
(bit 15) should be set in CRS0. So we have to clear that bit as well.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---

diff --git a/hw/pcnet.c b/hw/pcnet.c
index c53f06e..7413409 100644
--- a/hw/pcnet.c
+++ b/hw/pcnet.c
@@ -884,7 +884,7 @@ static void pcnet_stop(PCNetState *s)
 #ifdef PCNET_DEBUG
     printf("pcnet_stop\n");
 #endif
-    s->csr[0] &= ~0x7feb;
+    s->csr[0] &= ~0xffeb;
     s->csr[0] |= 0x0014;
     s->csr[4] &= ~0x02c2;
     s->csr[5] &= ~0x0011;