From: Marek Olšák <marek.olsak@amd.com>
Date: Wed, 8 Feb 2017 02:01:32 +0000 (+0100)
Subject: radeonsi: remove separate CB/DB_META flush flags
X-Git-Tag: upstream/17.1.0~2389
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=65df38b191b107a9ff917ae3cf9b2f0ca2d15627;p=platform%2Fupstream%2Fmesa.git

radeonsi: remove separate CB/DB_META flush flags

not used separately

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
---

diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index e198765..540f946 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -117,8 +117,7 @@ static unsigned get_flush_flags(struct si_context *sctx, enum r600_coherency coh
 		       SI_CONTEXT_INV_VMEM_L1 |
 		       (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
 	case R600_COHERENCY_CB_META:
-		return SI_CONTEXT_FLUSH_AND_INV_CB |
-		       SI_CONTEXT_FLUSH_AND_INV_CB_META;
+		return SI_CONTEXT_FLUSH_AND_INV_CB;
 	}
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index d17d55a..4075d2c 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -53,9 +53,8 @@
 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2	(R600_CONTEXT_PRIVATE_FLAG << 4)
+/* gaps */
 /* Framebuffer caches. */
-#define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
-#define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 6)
 #define SI_CONTEXT_FLUSH_AND_INV_DB	(R600_CONTEXT_PRIVATE_FLAG << 7)
 #define SI_CONTEXT_FLUSH_AND_INV_CB	(R600_CONTEXT_PRIVATE_FLAG << 8)
 /* Engine synchronization. */
@@ -66,9 +65,7 @@
 #define SI_CONTEXT_VGT_STREAMOUT_SYNC	(R600_CONTEXT_PRIVATE_FLAG << 13)
 
 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
-					      SI_CONTEXT_FLUSH_AND_INV_CB_META | \
-					      SI_CONTEXT_FLUSH_AND_INV_DB | \
-					      SI_CONTEXT_FLUSH_AND_INV_DB_META)
+					      SI_CONTEXT_FLUSH_AND_INV_DB)
 
 #define SI_MAX_BORDER_COLORS	4096
 
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index b6bd3f1..b6cf9a7 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -780,23 +780,18 @@ void si_emit_cache_flush(struct si_context *sctx)
 		if (rctx->chip_class == VI)
 			r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
 						 0, 0, NULL, 0, 0, 0);
+
+		/* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
+		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+		radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
 	}
 	if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
 		cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
 				 S_0085F0_DB_DEST_BASE_ENA(1);
-	}
 
-	if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
-		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
-		radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
-		/* needed for wait for idle in SURFACE_SYNC */
-		assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
-	}
-	if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
+		/* Flush HTILE. SURFACE_SYNC will wait for idle. */
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 		radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
-		/* needed for wait for idle in SURFACE_SYNC */
-		assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
 	}
 
 	/* Wait for shader engines to go idle.