From: ziv.xu <ziv.xu@starfive.com>
Date: Thu, 2 Mar 2023 07:01:47 +0000 (+0800)
Subject: thermal: enable thermal subsystem with step_wise governor
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=65c16cb65616c36406737524c08efcdbb33aaacc;p=platform%2Fkernel%2Flinux-starfive.git

thermal: enable thermal subsystem with step_wise governor

enable thermal subsystem with step_wise governor

Signed-off-by: ziv.xu <ziv.xu@starfive.com>
---

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 7696b07..08b4280 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/clock/starfive-jh7110-vout.h>
 #include <dt-bindings/clock/starfive-jh7110-isp.h>
 #include <dt-bindings/power/jh7110-power.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	compatible = "starfive,jh7110";
@@ -61,6 +62,7 @@
 			next-level-cache = <&cachectrl>;
 			riscv,isa = "rv64imac";
 			tlb-split;
+			#cooling-cells = <2>;
 			status = "disabled";
 
 			cpu0intctrl: interrupt-controller {
@@ -88,6 +90,7 @@
 			next-level-cache = <&cachectrl>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			#cooling-cells = <2>;
 			status = "okay";
 			operating-points-v2 = <&cluster0_opp>;
 
@@ -116,6 +119,7 @@
 			next-level-cache = <&cachectrl>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			#cooling-cells = <2>;
 			status = "okay";
 			operating-points-v2 = <&cluster0_opp>;
 
@@ -144,6 +148,7 @@
 			next-level-cache = <&cachectrl>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			#cooling-cells = <2>;
 			status = "okay";
 			operating-points-v2 = <&cluster0_opp>;
 
@@ -172,6 +177,7 @@
 			next-level-cache = <&cachectrl>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			#cooling-cells = <2>;
 			status = "okay";
 			operating-points-v2 = <&cluster0_opp>;
 
@@ -640,9 +646,6 @@
 
 				thermal-sensors = <&sfctemp>;
 
-				cooling-maps {
-				};
-
 				trips {
 					cpu_alert0: cpu_alert0 {
 						/* milliCelsius */
@@ -658,6 +661,17 @@
 						type = "critical";
 					};
 				};
+
+				cooling-maps {
+					map0 {
+						trip = <&cpu_alert0>;
+						cooling-device =
+							<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					};
+				};
 			};
 		};
 
diff --git a/arch/riscv/configs/starfive_jh7110_defconfig b/arch/riscv/configs/starfive_jh7110_defconfig
index 760c09b..0f5c525 100644
--- a/arch/riscv/configs/starfive_jh7110_defconfig
+++ b/arch/riscv/configs/starfive_jh7110_defconfig
@@ -1,3 +1,5 @@
+CONFIG_COMPILE_TEST=y
+# CONFIG_WERROR is not set
 CONFIG_DEFAULT_HOSTNAME="StarFive"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
@@ -26,6 +28,7 @@ CONFIG_PM_STD_PARTITION="PARTLABEL=hibernation"
 CONFIG_PM_DEBUG=y
 CONFIG_PM_ADVANCED_DEBUG=y
 CONFIG_PM_TEST_SUSPEND=y
+CONFIG_ENERGY_MODEL=y
 CONFIG_CPU_IDLE=y
 CONFIG_RISCV_SBI_CPUIDLE=y
 # CONFIG_SECCOMP is not set
@@ -184,6 +187,10 @@ CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_SYSCON=y
 CONFIG_POWER_RESET_SYSCON_POWEROFF=y
 CONFIG_SENSORS_SFCTEMP=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_SYSFS=y
 CONFIG_STARFIVE_WATCHDOG=y