From: Francisco Jerez Date: Sat, 16 Jul 2022 02:11:04 +0000 (-0700) Subject: intel/eu/xe2+: Update validation of GRF region size to account for Xe2 reg size X-Git-Tag: upstream/23.3.3~1807 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6423cb9bfa8972c21dcc00b3bfdc89560b855e71;p=platform%2Fupstream%2Fmesa.git intel/eu/xe2+: Update validation of GRF region size to account for Xe2 reg size Reviewed-by: Caio Oliveira Reviewed-by: Jordan Justen Part-of: --- diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index cbcc94e..ec02cb2 100644 --- a/src/intel/compiler/brw_eu_validate.c +++ b/src/intel/compiler/brw_eu_validate.c @@ -1465,7 +1465,7 @@ region_alignment_rules(const struct brw_isa_info *isa, unsigned hstride_elements = (num_hstride - 1) * hstride; unsigned offset = (vstride_elements + hstride_elements) * element_size + subreg; - ERROR_IF(offset >= 64, + ERROR_IF(offset >= 64 * reg_unit(devinfo), "A source cannot span more than 2 adjacent GRF registers"); } @@ -1477,7 +1477,7 @@ region_alignment_rules(const struct brw_isa_info *isa, unsigned element_size = brw_reg_type_to_size(dst_type); unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); unsigned offset = ((exec_size - 1) * stride * element_size) + subreg; - ERROR_IF(offset >= 64, + ERROR_IF(offset >= 64 * reg_unit(devinfo), "A destination cannot span more than 2 adjacent GRF registers"); if (error_msg.str)