From: Craig Topper <craig.topper@sifive.com>
Date: Sun, 13 Nov 2022 19:52:14 +0000 (-0800)
Subject: [RISCV] Add BREV8 to hasAllWUsers in RISCVSExtWRemoval.
X-Git-Tag: upstream/17.0.6~27815
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6373f8c31720e7d9712acc5914ed9176df5dabde;p=platform%2Fupstream%2Fllvm.git

[RISCV] Add BREV8 to hasAllWUsers in RISCVSExtWRemoval.

This instruction reverses the bits in each byte. Since we're only
interested in whether the upper 32 bits are used or not, we can
look through them to check their users.
---

diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index 169d186..62154c7 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -198,6 +198,7 @@ static bool hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI) {
       case RISCV::XORI:
 
       case RISCV::ANDN:
+      case RISCV::BREV8:
       case RISCV::CLMUL:
       case RISCV::ORC_B:
       case RISCV::ORN: