From: Richard Earnshaw <rearnsha@arm.com>
Date: Thu, 20 Jan 2022 15:41:37 +0000 (+0000)
Subject:  aarch64: allow ld1/stq in test output [PR102517]
X-Git-Tag: upstream/12.2.0~1922
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=62eb400b51f8a552320a250b3ac0b5d2ebd8927f;p=platform%2Fupstream%2Fgcc.git

 aarch64: allow ld1/stq in test output [PR102517]

Following the changes to the inline memcpy operations get expanded, we
now generate ld1/st1 using a 128-bit vector register rather than ldp
with Q registers.  The behaviour is equivalent, so relax the tests to
permit either variant.

gcc/testsuite/ChangeLog:

	PR target/102517
	* gcc.target/aarch64/cpymem-q-reg_1.c: Allow ld1 and st1 for the
	memcpy expansion.
---

diff --git a/gcc/testsuite/gcc.target/aarch64/cpymem-q-reg_1.c b/gcc/testsuite/gcc.target/aarch64/cpymem-q-reg_1.c
index df5f67e..45f3f0a 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpymem-q-reg_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpymem-q-reg_1.c
@@ -10,7 +10,7 @@ foo (void)
   __builtin_memcpy (dst, src, N * sizeof (int));
 }
 
-/* { dg-final { scan-assembler {ldp\tq[0-9]*} } } */
+/* { dg-final { scan-assembler {ldp\tq[0-9]*|ld1\t{v[0-9]*\.16b - v[0-9]*\.16b}} } } */
 /* { dg-final { scan-assembler-not {ldp\tx[0-9]*} } } */
-/* { dg-final { scan-assembler {stp\tq[0-9]*} } } */
+/* { dg-final { scan-assembler {stp\tq[0-9]*|st1\t{v[0-9]*\.16b - v[0-9]*\.16b}} } } */
 /* { dg-final { scan-assembler-not {stp\tx[0-9]*} } } */