From: Jernej Skrabec Date: Wed, 6 Jan 2021 18:19:01 +0000 (+0100) Subject: ARM: dts: sun8i: r40: Add deinterlace node X-Git-Tag: v5.15~1797^2~36^2~33 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=62de535663e8bf4a5442bb11de7e4926a00eb93c;p=platform%2Fkernel%2Flinux-starfive.git ARM: dts: sun8i: r40: Add deinterlace node R40 contains deinterlace core compatible to that in H3. One peculiarity is that RAM gate is shared with CSI1. User manual states it's separate but that's not true. Shared gate was verified with BSP Linux code check and with runtime tests (CPU crashed if CSI1 gate was not ungated). Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210106181901.1324075-3-jernej.skrabec@siol.net --- diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 7907569..d5ad3b9 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -190,6 +190,25 @@ }; }; + deinterlace: deinterlace@1400000 { + compatible = "allwinner,sun8i-r40-deinterlace", + "allwinner,sun8i-h3-deinterlace"; + reg = <0x01400000 0x20000>; + clocks = <&ccu CLK_BUS_DEINTERLACE>, + <&ccu CLK_DEINTERLACE>, + /* + * NOTE: Contrary to what datasheet claims, + * DRAM deinterlace gate doesn't exist and + * it's shared with CSI1. + */ + <&ccu CLK_DRAM_CSI1>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_DEINTERLACE>; + interrupts = ; + interconnects = <&mbus 9>; + interconnect-names = "dma-mem"; + }; + syscon: system-control@1c00000 { compatible = "allwinner,sun8i-r40-system-control", "allwinner,sun4i-a10-system-control";