From: Zi Xuan Wu (Zeson) Date: Mon, 12 Dec 2022 03:23:17 +0000 (+0800) Subject: [CSKY][NFC] Fix check-all error due to change of expected output X-Git-Tag: upstream/17.0.6~24297 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=62c4dce5b4b9eef0608635aef12aac85f3ab9596;p=platform%2Fupstream%2Fllvm.git [CSKY][NFC] Fix check-all error due to change of expected output - Remove unnecessary symbol offset check in MC cases. - Change other expected output in CodeGen cases. --- diff --git a/llvm/test/CodeGen/CSKY/br.ll b/llvm/test/CodeGen/CSKY/br.ll index d4a1e57..f6b9a6c 100644 --- a/llvm/test/CodeGen/CSKY/br.ll +++ b/llvm/test/CodeGen/CSKY/br.ll @@ -2409,10 +2409,7 @@ define i64 @brR0_i64_sge(i64 %x) { ; GENERIC-NEXT: bt16 .LBB50_2 ; GENERIC-NEXT: # %bb.1: # %label1 ; GENERIC-NEXT: movi16 a0, 1 -; GENERIC-NEXT: br32 .LBB50_3 ; GENERIC-NEXT: .LBB50_2: # %label2 -; GENERIC-NEXT: movi16 a0, 0 -; GENERIC-NEXT: .LBB50_3: # %label1 ; GENERIC-NEXT: movi16 a1, 0 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 @@ -5868,9 +5865,7 @@ define i1 @brRI_i1_uge(i1 %x) { ; CHECK-NEXT: bt32 .LBB126_2 ; CHECK-NEXT: # %bb.1: # %label1 ; CHECK-NEXT: movi16 a0, 1 -; CHECK-NEXT: rts16 ; CHECK-NEXT: .LBB126_2: # %label2 -; CHECK-NEXT: movi16 a0, 0 ; CHECK-NEXT: rts16 ; ; GENERIC-LABEL: brRI_i1_uge: @@ -5883,10 +5878,7 @@ define i1 @brRI_i1_uge(i1 %x) { ; GENERIC-NEXT: bt16 .LBB126_2 ; GENERIC-NEXT: # %bb.1: # %label1 ; GENERIC-NEXT: movi16 a0, 1 -; GENERIC-NEXT: addi16 sp, sp, 4 -; GENERIC-NEXT: rts16 ; GENERIC-NEXT: .LBB126_2: # %label2 -; GENERIC-NEXT: movi16 a0, 0 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 ; CHECK-UGTXT: icmpu32 a0, a1, a0 @@ -5951,7 +5943,6 @@ define i1 @brRI_i1_ult(i1 %x) { ; CHECK-NEXT: btsti16 a0, 0 ; CHECK-NEXT: bt32 .LBB128_2 ; CHECK-NEXT: # %bb.1: # %label1 -; CHECK-NEXT: movi16 a0, 1 ; CHECK-NEXT: rts16 ; CHECK-NEXT: .LBB128_2: # %label2 ; CHECK-NEXT: movi16 a0, 0 @@ -5966,7 +5957,6 @@ define i1 @brRI_i1_ult(i1 %x) { ; GENERIC-NEXT: btsti16 a0, 0 ; GENERIC-NEXT: bt16 .LBB128_2 ; GENERIC-NEXT: # %bb.1: # %label1 -; GENERIC-NEXT: movi16 a0, 1 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 ; GENERIC-NEXT: .LBB128_2: # %label2 @@ -6163,7 +6153,6 @@ define i1 @brRI_i1_sgt(i1 %x) { ; CHECK-NEXT: btsti16 a0, 0 ; CHECK-NEXT: bt32 .LBB133_2 ; CHECK-NEXT: # %bb.1: # %label1 -; CHECK-NEXT: movi16 a0, 1 ; CHECK-NEXT: rts16 ; CHECK-NEXT: .LBB133_2: # %label2 ; CHECK-NEXT: movi16 a0, 0 @@ -6178,7 +6167,6 @@ define i1 @brRI_i1_sgt(i1 %x) { ; GENERIC-NEXT: btsti16 a0, 0 ; GENERIC-NEXT: bt16 .LBB133_2 ; GENERIC-NEXT: # %bb.1: # %label1 -; GENERIC-NEXT: movi16 a0, 1 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 ; GENERIC-NEXT: .LBB133_2: # %label2 @@ -6203,7 +6191,6 @@ define i1 @brR0_i1_sgt(i1 %x) { ; CHECK-NEXT: btsti16 a0, 0 ; CHECK-NEXT: bt32 .LBB134_2 ; CHECK-NEXT: # %bb.1: # %label1 -; CHECK-NEXT: movi16 a0, 1 ; CHECK-NEXT: rts16 ; CHECK-NEXT: .LBB134_2: # %label2 ; CHECK-NEXT: movi16 a0, 0 @@ -6218,7 +6205,6 @@ define i1 @brR0_i1_sgt(i1 %x) { ; GENERIC-NEXT: btsti16 a0, 0 ; GENERIC-NEXT: bt16 .LBB134_2 ; GENERIC-NEXT: # %bb.1: # %label1 -; GENERIC-NEXT: movi16 a0, 1 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 ; GENERIC-NEXT: .LBB134_2: # %label2 @@ -6541,9 +6527,7 @@ define i1 @brRI_i1_sle(i1 %x) { ; CHECK-NEXT: bt32 .LBB142_2 ; CHECK-NEXT: # %bb.1: # %label1 ; CHECK-NEXT: movi16 a0, 1 -; CHECK-NEXT: rts16 ; CHECK-NEXT: .LBB142_2: # %label2 -; CHECK-NEXT: movi16 a0, 0 ; CHECK-NEXT: rts16 ; ; GENERIC-LABEL: brRI_i1_sle: @@ -6556,10 +6540,7 @@ define i1 @brRI_i1_sle(i1 %x) { ; GENERIC-NEXT: bt16 .LBB142_2 ; GENERIC-NEXT: # %bb.1: # %label1 ; GENERIC-NEXT: movi16 a0, 1 -; GENERIC-NEXT: addi16 sp, sp, 4 -; GENERIC-NEXT: rts16 ; GENERIC-NEXT: .LBB142_2: # %label2 -; GENERIC-NEXT: movi16 a0, 0 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 ; CHECK-UGTXT: icmpu32 a0, a1, a0 @@ -6581,9 +6562,7 @@ define i1 @brR0_i1_sle(i1 %x) { ; CHECK-NEXT: bt32 .LBB143_2 ; CHECK-NEXT: # %bb.1: # %label1 ; CHECK-NEXT: movi16 a0, 1 -; CHECK-NEXT: rts16 ; CHECK-NEXT: .LBB143_2: # %label2 -; CHECK-NEXT: movi16 a0, 0 ; CHECK-NEXT: rts16 ; ; GENERIC-LABEL: brR0_i1_sle: @@ -6596,10 +6575,7 @@ define i1 @brR0_i1_sle(i1 %x) { ; GENERIC-NEXT: bt16 .LBB143_2 ; GENERIC-NEXT: # %bb.1: # %label1 ; GENERIC-NEXT: movi16 a0, 1 -; GENERIC-NEXT: addi16 sp, sp, 4 -; GENERIC-NEXT: rts16 ; GENERIC-NEXT: .LBB143_2: # %label2 -; GENERIC-NEXT: movi16 a0, 0 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 ; CHECK-UGTXT: icmpu32 a0, a1, a0 diff --git a/llvm/test/CodeGen/CSKY/fpu/br-d.ll b/llvm/test/CodeGen/CSKY/fpu/br-d.ll index 95e7d072..cc278d3 100644 --- a/llvm/test/CodeGen/CSKY/fpu/br-d.ll +++ b/llvm/test/CodeGen/CSKY/fpu/br-d.ll @@ -53,7 +53,7 @@ define i32 @brRI_oeq(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI1_0: ; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10 ; @@ -70,7 +70,7 @@ define i32 @brRI_oeq(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI1_0: ; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10 entry: @@ -99,7 +99,7 @@ define i32 @brR0_oeq(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI2_0: ; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 ; @@ -116,7 +116,7 @@ define i32 @brR0_oeq(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI2_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: @@ -194,7 +194,7 @@ define i32 @brRI_one(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI4_0: ; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10 ; @@ -216,7 +216,7 @@ define i32 @brRI_one(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI4_0: ; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10 entry: @@ -250,7 +250,7 @@ define i32 @brR0_one(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI5_0: ; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 ; @@ -272,7 +272,7 @@ define i32 @brR0_one(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI5_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: @@ -335,7 +335,7 @@ define i32 @brRI_ugt(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI7_0: ; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10 ; @@ -352,7 +352,7 @@ define i32 @brRI_ugt(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI7_0: ; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10 entry: @@ -381,7 +381,7 @@ define i32 @brR0_ugt(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI8_0: ; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 ; @@ -398,7 +398,7 @@ define i32 @brR0_ugt(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI8_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: @@ -461,7 +461,7 @@ define i32 @brRI_uge(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI10_0: ; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10 ; @@ -478,7 +478,7 @@ define i32 @brRI_uge(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI10_0: ; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10 entry: @@ -507,7 +507,7 @@ define i32 @brR0_uge(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI11_0: ; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 ; @@ -524,7 +524,7 @@ define i32 @brR0_uge(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI11_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: @@ -587,7 +587,7 @@ define i32 @brRI_ult(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI13_0: ; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10 ; @@ -604,7 +604,7 @@ define i32 @brRI_ult(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI13_0: ; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10 entry: @@ -633,7 +633,7 @@ define i32 @brR0_ult(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI14_0: ; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 ; @@ -650,7 +650,7 @@ define i32 @brR0_ult(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI14_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: @@ -713,7 +713,7 @@ define i32 @brRI_ule(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI16_0: ; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10 ; @@ -730,7 +730,7 @@ define i32 @brRI_ule(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI16_0: ; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10 entry: @@ -759,7 +759,7 @@ define i32 @brR0_ule(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI17_0: ; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 ; @@ -776,7 +776,7 @@ define i32 @brR0_ule(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI17_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: @@ -848,7 +848,7 @@ define i32 @brRI_ogt(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI19_0: ; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10 ; @@ -868,7 +868,7 @@ define i32 @brRI_ogt(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI19_0: ; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10 entry: @@ -900,7 +900,7 @@ define i32 @brR0_ogt(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI20_0: ; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 ; @@ -920,7 +920,7 @@ define i32 @brR0_ogt(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI20_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: @@ -992,7 +992,7 @@ define i32 @brRI_oge(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI22_0: ; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10 ; @@ -1012,7 +1012,7 @@ define i32 @brRI_oge(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI22_0: ; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10 entry: @@ -1044,7 +1044,7 @@ define i32 @brR0_oge(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI23_0: ; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 ; @@ -1064,7 +1064,7 @@ define i32 @brR0_oge(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI23_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: @@ -1136,7 +1136,7 @@ define i32 @brRI_olt(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI25_0: ; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10 ; @@ -1156,7 +1156,7 @@ define i32 @brRI_olt(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI25_0: ; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10 entry: @@ -1188,7 +1188,7 @@ define i32 @brR0_olt(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI26_0: ; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 ; @@ -1208,7 +1208,7 @@ define i32 @brR0_olt(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI26_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: @@ -1280,7 +1280,7 @@ define i32 @brRI_ole(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI28_0: ; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10 ; @@ -1300,7 +1300,7 @@ define i32 @brRI_ole(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI28_0: ; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10 entry: @@ -1332,7 +1332,7 @@ define i32 @brR0_ole(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI29_0: ; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 ; @@ -1352,7 +1352,7 @@ define i32 @brR0_ole(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI29_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: @@ -1374,7 +1374,6 @@ define i32 @brRR_false(double %x, double %y) { ; CHECK-DF-NEXT: btsti16 a0, 0 ; CHECK-DF-NEXT: bt32 .LBB30_2 ; CHECK-DF-NEXT: # %bb.1: # %label1 -; CHECK-DF-NEXT: movi16 a0, 1 ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .LBB30_2: # %label2 ; CHECK-DF-NEXT: movi16 a0, 0 @@ -1386,7 +1385,6 @@ define i32 @brRR_false(double %x, double %y) { ; CHECK-DF2-NEXT: btsti16 a0, 0 ; CHECK-DF2-NEXT: bt32 .LBB30_2 ; CHECK-DF2-NEXT: # %bb.1: # %label1 -; CHECK-DF2-NEXT: movi16 a0, 1 ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .LBB30_2: # %label2 ; CHECK-DF2-NEXT: movi16 a0, 0 @@ -1409,7 +1407,6 @@ define i32 @brRI_false(double %x) { ; CHECK-DF-NEXT: btsti16 a0, 0 ; CHECK-DF-NEXT: bt32 .LBB31_2 ; CHECK-DF-NEXT: # %bb.1: # %label1 -; CHECK-DF-NEXT: movi16 a0, 1 ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .LBB31_2: # %label2 ; CHECK-DF-NEXT: movi16 a0, 0 @@ -1421,7 +1418,6 @@ define i32 @brRI_false(double %x) { ; CHECK-DF2-NEXT: btsti16 a0, 0 ; CHECK-DF2-NEXT: bt32 .LBB31_2 ; CHECK-DF2-NEXT: # %bb.1: # %label1 -; CHECK-DF2-NEXT: movi16 a0, 1 ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .LBB31_2: # %label2 ; CHECK-DF2-NEXT: movi16 a0, 0 @@ -1444,7 +1440,6 @@ define i32 @brR0_false(double %x) { ; CHECK-DF-NEXT: btsti16 a0, 0 ; CHECK-DF-NEXT: bt32 .LBB32_2 ; CHECK-DF-NEXT: # %bb.1: # %label1 -; CHECK-DF-NEXT: movi16 a0, 1 ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .LBB32_2: # %label2 ; CHECK-DF-NEXT: movi16 a0, 0 @@ -1456,7 +1451,6 @@ define i32 @brR0_false(double %x) { ; CHECK-DF2-NEXT: btsti16 a0, 0 ; CHECK-DF2-NEXT: bt32 .LBB32_2 ; CHECK-DF2-NEXT: # %bb.1: # %label1 -; CHECK-DF2-NEXT: movi16 a0, 1 ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .LBB32_2: # %label2 ; CHECK-DF2-NEXT: movi16 a0, 0 @@ -1638,7 +1632,7 @@ define i32 @brRI_ueq(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI37_0: ; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10 ; @@ -1660,7 +1654,7 @@ define i32 @brRI_ueq(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI37_0: ; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10 entry: @@ -1694,7 +1688,7 @@ define i32 @brR0_ueq(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI38_0: ; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 ; @@ -1716,7 +1710,7 @@ define i32 @brR0_ueq(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI38_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: @@ -1779,7 +1773,7 @@ define i32 @brRI_une(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI40_0: ; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10 ; @@ -1796,7 +1790,7 @@ define i32 @brRI_une(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI40_0: ; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10 entry: @@ -1825,7 +1819,7 @@ define i32 @brR0_une(double %x) { ; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .p2align 1 ; CHECK-DF-NEXT: # %bb.3: -; CHECK-DF-NEXT: .p2align 2 +; CHECK-DF-NEXT: .p2align 2, 0x0 ; CHECK-DF-NEXT: .LCPI41_0: ; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 ; @@ -1842,7 +1836,7 @@ define i32 @brR0_une(double %x) { ; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .p2align 1 ; CHECK-DF2-NEXT: # %bb.3: -; CHECK-DF2-NEXT: .p2align 2 +; CHECK-DF2-NEXT: .p2align 2, 0x0 ; CHECK-DF2-NEXT: .LCPI41_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: @@ -1965,9 +1959,7 @@ define i32 @brRR_true(double %x, double %y) { ; CHECK-DF-NEXT: bt32 .LBB45_2 ; CHECK-DF-NEXT: # %bb.1: # %label1 ; CHECK-DF-NEXT: movi16 a0, 1 -; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .LBB45_2: # %label2 -; CHECK-DF-NEXT: movi16 a0, 0 ; CHECK-DF-NEXT: rts16 ; ; CHECK-DF2-LABEL: brRR_true: @@ -1977,9 +1969,7 @@ define i32 @brRR_true(double %x, double %y) { ; CHECK-DF2-NEXT: bt32 .LBB45_2 ; CHECK-DF2-NEXT: # %bb.1: # %label1 ; CHECK-DF2-NEXT: movi16 a0, 1 -; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .LBB45_2: # %label2 -; CHECK-DF2-NEXT: movi16 a0, 0 ; CHECK-DF2-NEXT: rts16 entry: %fcmp = fcmp true double %y, %x @@ -2000,9 +1990,7 @@ define i32 @brRI_true(double %x) { ; CHECK-DF-NEXT: bt32 .LBB46_2 ; CHECK-DF-NEXT: # %bb.1: # %label1 ; CHECK-DF-NEXT: movi16 a0, 1 -; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .LBB46_2: # %label2 -; CHECK-DF-NEXT: movi16 a0, 0 ; CHECK-DF-NEXT: rts16 ; ; CHECK-DF2-LABEL: brRI_true: @@ -2012,9 +2000,7 @@ define i32 @brRI_true(double %x) { ; CHECK-DF2-NEXT: bt32 .LBB46_2 ; CHECK-DF2-NEXT: # %bb.1: # %label1 ; CHECK-DF2-NEXT: movi16 a0, 1 -; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .LBB46_2: # %label2 -; CHECK-DF2-NEXT: movi16 a0, 0 ; CHECK-DF2-NEXT: rts16 entry: %fcmp = fcmp true double %x, 10.0 @@ -2035,9 +2021,7 @@ define i32 @brR0_true(double %x) { ; CHECK-DF-NEXT: bt32 .LBB47_2 ; CHECK-DF-NEXT: # %bb.1: # %label1 ; CHECK-DF-NEXT: movi16 a0, 1 -; CHECK-DF-NEXT: rts16 ; CHECK-DF-NEXT: .LBB47_2: # %label2 -; CHECK-DF-NEXT: movi16 a0, 0 ; CHECK-DF-NEXT: rts16 ; ; CHECK-DF2-LABEL: brR0_true: @@ -2047,9 +2031,7 @@ define i32 @brR0_true(double %x) { ; CHECK-DF2-NEXT: bt32 .LBB47_2 ; CHECK-DF2-NEXT: # %bb.1: # %label1 ; CHECK-DF2-NEXT: movi16 a0, 1 -; CHECK-DF2-NEXT: rts16 ; CHECK-DF2-NEXT: .LBB47_2: # %label2 -; CHECK-DF2-NEXT: movi16 a0, 0 ; CHECK-DF2-NEXT: rts16 entry: %fcmp = fcmp true double %x, 0.0 diff --git a/llvm/test/CodeGen/CSKY/fpu/br-f.ll b/llvm/test/CodeGen/CSKY/fpu/br-f.ll index cf9617d..7e08e7c 100644 --- a/llvm/test/CodeGen/CSKY/fpu/br-f.ll +++ b/llvm/test/CodeGen/CSKY/fpu/br-f.ll @@ -1123,7 +1123,6 @@ define i32 @brRR_false(float %x, float %y) { ; CHECK-SF-NEXT: btsti16 a0, 0 ; CHECK-SF-NEXT: bt32 .LBB30_2 ; CHECK-SF-NEXT: # %bb.1: # %label1 -; CHECK-SF-NEXT: movi16 a0, 1 ; CHECK-SF-NEXT: rts16 ; CHECK-SF-NEXT: .LBB30_2: # %label2 ; CHECK-SF-NEXT: movi16 a0, 0 @@ -1135,7 +1134,6 @@ define i32 @brRR_false(float %x, float %y) { ; CHECK-SF2-NEXT: btsti16 a0, 0 ; CHECK-SF2-NEXT: bt32 .LBB30_2 ; CHECK-SF2-NEXT: # %bb.1: # %label1 -; CHECK-SF2-NEXT: movi16 a0, 1 ; CHECK-SF2-NEXT: rts16 ; CHECK-SF2-NEXT: .LBB30_2: # %label2 ; CHECK-SF2-NEXT: movi16 a0, 0 @@ -1157,7 +1155,6 @@ define i32 @brRI_false(float %x) { ; CHECK-SF-NEXT: btsti16 a0, 0 ; CHECK-SF-NEXT: bt32 .LBB31_2 ; CHECK-SF-NEXT: # %bb.1: # %label1 -; CHECK-SF-NEXT: movi16 a0, 1 ; CHECK-SF-NEXT: rts16 ; CHECK-SF-NEXT: .LBB31_2: # %label2 ; CHECK-SF-NEXT: movi16 a0, 0 @@ -1169,7 +1166,6 @@ define i32 @brRI_false(float %x) { ; CHECK-SF2-NEXT: btsti16 a0, 0 ; CHECK-SF2-NEXT: bt32 .LBB31_2 ; CHECK-SF2-NEXT: # %bb.1: # %label1 -; CHECK-SF2-NEXT: movi16 a0, 1 ; CHECK-SF2-NEXT: rts16 ; CHECK-SF2-NEXT: .LBB31_2: # %label2 ; CHECK-SF2-NEXT: movi16 a0, 0 @@ -1191,7 +1187,6 @@ define i32 @brR0_false(float %x) { ; CHECK-SF-NEXT: btsti16 a0, 0 ; CHECK-SF-NEXT: bt32 .LBB32_2 ; CHECK-SF-NEXT: # %bb.1: # %label1 -; CHECK-SF-NEXT: movi16 a0, 1 ; CHECK-SF-NEXT: rts16 ; CHECK-SF-NEXT: .LBB32_2: # %label2 ; CHECK-SF-NEXT: movi16 a0, 0 @@ -1203,7 +1198,6 @@ define i32 @brR0_false(float %x) { ; CHECK-SF2-NEXT: btsti16 a0, 0 ; CHECK-SF2-NEXT: bt32 .LBB32_2 ; CHECK-SF2-NEXT: # %bb.1: # %label1 -; CHECK-SF2-NEXT: movi16 a0, 1 ; CHECK-SF2-NEXT: rts16 ; CHECK-SF2-NEXT: .LBB32_2: # %label2 ; CHECK-SF2-NEXT: movi16 a0, 0 @@ -1657,9 +1651,7 @@ define i32 @brRR_true(float %x, float %y) { ; CHECK-SF-NEXT: bt32 .LBB45_2 ; CHECK-SF-NEXT: # %bb.1: # %label1 ; CHECK-SF-NEXT: movi16 a0, 1 -; CHECK-SF-NEXT: rts16 ; CHECK-SF-NEXT: .LBB45_2: # %label2 -; CHECK-SF-NEXT: movi16 a0, 0 ; CHECK-SF-NEXT: rts16 ; ; CHECK-SF2-LABEL: brRR_true: @@ -1669,9 +1661,7 @@ define i32 @brRR_true(float %x, float %y) { ; CHECK-SF2-NEXT: bt32 .LBB45_2 ; CHECK-SF2-NEXT: # %bb.1: # %label1 ; CHECK-SF2-NEXT: movi16 a0, 1 -; CHECK-SF2-NEXT: rts16 ; CHECK-SF2-NEXT: .LBB45_2: # %label2 -; CHECK-SF2-NEXT: movi16 a0, 0 ; CHECK-SF2-NEXT: rts16 entry: %fcmp = fcmp true float %y, %x @@ -1691,9 +1681,7 @@ define i32 @brRI_true(float %x) { ; CHECK-SF-NEXT: bt32 .LBB46_2 ; CHECK-SF-NEXT: # %bb.1: # %label1 ; CHECK-SF-NEXT: movi16 a0, 1 -; CHECK-SF-NEXT: rts16 ; CHECK-SF-NEXT: .LBB46_2: # %label2 -; CHECK-SF-NEXT: movi16 a0, 0 ; CHECK-SF-NEXT: rts16 ; ; CHECK-SF2-LABEL: brRI_true: @@ -1703,9 +1691,7 @@ define i32 @brRI_true(float %x) { ; CHECK-SF2-NEXT: bt32 .LBB46_2 ; CHECK-SF2-NEXT: # %bb.1: # %label1 ; CHECK-SF2-NEXT: movi16 a0, 1 -; CHECK-SF2-NEXT: rts16 ; CHECK-SF2-NEXT: .LBB46_2: # %label2 -; CHECK-SF2-NEXT: movi16 a0, 0 ; CHECK-SF2-NEXT: rts16 entry: %fcmp = fcmp true float %x, 10.0 @@ -1725,9 +1711,7 @@ define i32 @brR0_true(float %x) { ; CHECK-SF-NEXT: bt32 .LBB47_2 ; CHECK-SF-NEXT: # %bb.1: # %label1 ; CHECK-SF-NEXT: movi16 a0, 1 -; CHECK-SF-NEXT: rts16 ; CHECK-SF-NEXT: .LBB47_2: # %label2 -; CHECK-SF-NEXT: movi16 a0, 0 ; CHECK-SF-NEXT: rts16 ; ; CHECK-SF2-LABEL: brR0_true: @@ -1737,9 +1721,7 @@ define i32 @brR0_true(float %x) { ; CHECK-SF2-NEXT: bt32 .LBB47_2 ; CHECK-SF2-NEXT: # %bb.1: # %label1 ; CHECK-SF2-NEXT: movi16 a0, 1 -; CHECK-SF2-NEXT: rts16 ; CHECK-SF2-NEXT: .LBB47_2: # %label2 -; CHECK-SF2-NEXT: movi16 a0, 0 ; CHECK-SF2-NEXT: rts16 entry: %fcmp = fcmp true float %x, 0.0 diff --git a/llvm/test/DebugInfo/CSKY/dwarf-csky-relocs.ll b/llvm/test/DebugInfo/CSKY/dwarf-csky-relocs.ll index e1f577a..e6c6946 100644 --- a/llvm/test/DebugInfo/CSKY/dwarf-csky-relocs.ll +++ b/llvm/test/DebugInfo/CSKY/dwarf-csky-relocs.ll @@ -40,7 +40,7 @@ ; DWARF-DUMP: .debug_line contents: ; DWARF-DUMP-NEXT: debug_line[0x00000000] ; DWARF-DUMP-NEXT: Line table prologue: -; DWARF-DUMP-NEXT: total_length: 0x00000059 +; DWARF-DUMP-NEXT: total_length: 0x0000005c ; DWARF-DUMP-NEXT: format: DWARF32 ; DWARF-DUMP-NEXT: version: 5 ; DWARF-DUMP-NEXT: address_size: 4 @@ -75,7 +75,8 @@ ; DWARF-DUMP-NEXT: ------------------ ------ ------ ------ --- ------------- ------------- ; DWARF-DUMP-NEXT: 0x0000000000000000 2 0 0 0 0 is_stmt ; DWARF-DUMP-NEXT: 0x000000000000000e 3 3 0 0 0 is_stmt prologue_end -; DWARF-DUMP-NEXT: 0x000000000000001a 3 3 0 0 0 is_stmt end_sequence +; DWARF-DUMP-NEXT: 0x0000000000000016 3 3 0 0 0 epilogue_begin +; DWARF-DUMP-NEXT: 0x000000000000001a 3 3 0 0 0 end_sequence ; ModuleID = 'dwarf-csky-relocs.c' source_filename = "dwarf-csky-relocs.c" diff --git a/llvm/test/MC/CSKY/branch-relax-803.s b/llvm/test/MC/CSKY/branch-relax-803.s index 6aacbe2..1591b43 100644 --- a/llvm/test/MC/CSKY/branch-relax-803.s +++ b/llvm/test/MC/CSKY/branch-relax-803.s @@ -4,15 +4,15 @@ # CHECK-OBJ-CK803: 0: addu16 r1, r2, r3 # CHECK-OBJ-CK803-NEXT: 2: bt16 0x8 -# CHECK-OBJ-CK803-NEXT: 4: jmpi32 0x3a9a0 <$d.0> -# CHECK-OBJ-CK803-NEXT: 8: bsr32 0x3a990 <.text+0x3a990> +# CHECK-OBJ-CK803-NEXT: 4: jmpi32 0x3a9a0 +# CHECK-OBJ-CK803-NEXT: 8: bsr32 0x3a990 # CHECK-OBJ-CK803-NEXT: c: addu16 r3, r2, r1 # CHECK-OBJ-CK803: 3a98e: addu16 r1, r2, r3 -# CHECK-OBJ-CK803-NEXT: 3a990: bf16 0x3a996 <.text+0x3a996> -# CHECK-OBJ-CK803-NEXT: 3a992: jmpi32 0x3a9a4 <$d.0+0x4> -# CHECK-OBJ-CK803-NEXT: 3a996: jmpi32 0x3a9a4 <$d.0+0x4> +# CHECK-OBJ-CK803-NEXT: 3a990: bf16 0x3a996 +# CHECK-OBJ-CK803-NEXT: 3a992: jmpi32 0x3a9a4 +# CHECK-OBJ-CK803-NEXT: 3a996: jmpi32 0x3a9a4 # CHECK-OBJ-CK803-NEXT: 3a99a: addu16 r3, r2, r1 -# CHECK-OBJ-CK803-NEXT: 3a99c: br16 0x3a99e <.text+0x3a99e> +# CHECK-OBJ-CK803-NEXT: 3a99c: br16 0x3a99e addu16 r1, r2, r3 diff --git a/llvm/test/MC/CSKY/jsri.s b/llvm/test/MC/CSKY/jsri.s index 8342f89..446cb85 100644 --- a/llvm/test/MC/CSKY/jsri.s +++ b/llvm/test/MC/CSKY/jsri.s @@ -26,15 +26,15 @@ tstart: jsri 0xFFFFFFFE -# CHECK: 0: jsri32 0x30 <$d.4> -# CHECK-NEXT: 4: jsri32 0x34 <$d.4+0x4> -# CHECK-NEXT: 8: jsri32 0x38 <$d.4+0x8> +# CHECK: 0: jsri32 0x30 +# CHECK-NEXT: 4: jsri32 0x34 +# CHECK-NEXT: 8: jsri32 0x38 # CHECK: c: 00 1c .short 0x1c00 -# CHECK: e: jsri32 0x3c <$d.4+0xc> -# CHECK-NEXT: 12: jsri32 0x40 <$d.4+0x10> -# CHECK-NEXT: 16: jsri32 0x44 <$d.4+0x14> +# CHECK: e: jsri32 0x3c +# CHECK-NEXT: 12: jsri32 0x40 +# CHECK-NEXT: 16: jsri32 0x44 @@ -42,12 +42,12 @@ tstart: # CHECK-NEXT: 1a: bsr32 0x1a # CHECK: <.J2>: -# CHECK-NEXT: 1e: bsr32 0xfffff01e <$d.4+0xffffffffffffefee> +# CHECK-NEXT: 1e: bsr32 0xfffff01e # CHECK: <.J3>: -# CHECK-NEXT: 22: bsr32 0x1022 <$d.4+0xff2> -# CHECK-NEXT: 26: jsri32 0x54 <$d.4+0x24> -# CHECK-NEXT: 2a: jsri32 0x58 <$d.4+0x28> +# CHECK-NEXT: 22: bsr32 0x1022 +# CHECK-NEXT: 26: jsri32 0x54 +# CHECK-NEXT: 2a: jsri32 0x58 # CHECK-NEXT: 2e: bkpt diff --git a/llvm/test/MC/CSKY/lrw.s b/llvm/test/MC/CSKY/lrw.s index 69eea7e..c05b2cd 100644 --- a/llvm/test/MC/CSKY/lrw.s +++ b/llvm/test/MC/CSKY/lrw.s @@ -29,24 +29,24 @@ tstart: lrw r0,0x01020304 lrw r0,0xFFFFFFFE -# CHECK: 0: lrw16 r0, 0x28 <$d.4> -# CHECK-NEXT: 2: lrw16 r0, 0x2c <$d.4+0x4> -# CHECK-NEXT: 4: lrw16 r0, 0x30 <$d.4+0x8> +# CHECK: 0: lrw16 r0, 0x28 +# CHECK-NEXT: 2: lrw16 r0, 0x2c +# CHECK-NEXT: 4: lrw16 r0, 0x30 # CHECK: 6: 00 1c .short 0x1c00 -# CHECK: 8: lrw16 r0, 0x34 <$d.4+0xc> -# CHECK-NEXT: a: lrw16 r0, 0x38 <$d.4+0x10> -# CHECK-NEXT: c: lrw16 r0, 0x3c <$d.4+0x14> +# CHECK: 8: lrw16 r0, 0x34 +# CHECK-NEXT: a: lrw16 r0, 0x38 +# CHECK-NEXT: c: lrw16 r0, 0x3c # CHECK-NEXT: e: movi16 r0, 0 # CHECK-NEXT: 10: movi32 r0, 65535 # CHECK-NEXT: 14: movi32 r31, 0 -# CHECK-NEXT: 18: lrw32 r31, 0x40 <$d.4+0x18> -# CHECK-NEXT: 1c: lrw16 r0, 0x44 <$d.4+0x1c> -# CHECK-NEXT: 1e: lrw16 r0, 0x48 <$d.4+0x20> -# CHECK-NEXT: 20: lrw16 r0, 0x4c <$d.4+0x24> -# CHECK-NEXT: 22: lrw16 r0, 0x50 <$d.4+0x28> -# CHECK-NEXT: 24: lrw16 r0, 0x54 <$d.4+0x2c> +# CHECK-NEXT: 18: lrw32 r31, 0x40 +# CHECK-NEXT: 1c: lrw16 r0, 0x44 +# CHECK-NEXT: 1e: lrw16 r0, 0x48 +# CHECK-NEXT: 20: lrw16 r0, 0x4c +# CHECK-NEXT: 22: lrw16 r0, 0x50 +# CHECK-NEXT: 24: lrw16 r0, 0x54 # CHECK: 28: 00 00 00 00 .word 0x00000000 # CHECK-NEXT: 00000028: R_CKCORE_ADDR32 lnk diff --git a/llvm/test/MC/CSKY/tls_gd.s b/llvm/test/MC/CSKY/tls_gd.s index 3e1cc06..5508edf 100644 --- a/llvm/test/MC/CSKY/tls_gd.s +++ b/llvm/test/MC/CSKY/tls_gd.s @@ -9,10 +9,10 @@ ldr32.w r3, (rgb, r3 << 0) jsr16 r3 -# CHECK: 0: lrw16 r0, 0x10 <$d.0> +# CHECK: 0: lrw16 r0, 0x10 # CHECK-NEXT: 2: grs32 r2, 0x0 # CHECK-NEXT: 6: addu16 r0, r0, r2 -# CHECK-NEXT: 8: lrw16 r3, 0x14 <$d.0+0x4> +# CHECK-NEXT: 8: lrw16 r3, 0x14 # CHECK-NEXT: a: ldr32.w r3, (r28, r3 << 0) # CHECK-NEXT: e: jsr16 r3 diff --git a/llvm/test/MC/CSKY/tls_ie.s b/llvm/test/MC/CSKY/tls_ie.s index 1752dfc..2119a7f 100644 --- a/llvm/test/MC/CSKY/tls_ie.s +++ b/llvm/test/MC/CSKY/tls_ie.s @@ -10,7 +10,7 @@ str32.w r0, (r2, r3 << 0) -# CHECK: 0: lrw16 r3, 0x14 <$d.0> +# CHECK: 0: lrw16 r3, 0x14 # CHECK-NEXT: 2: grs32 r2, 0x0 # CHECK-NEXT: 6: addu16 r3, r3, r2 # CHECK-NEXT: 8: ld16.w r3, (r3, 0x0) diff --git a/llvm/test/MC/CSKY/tls_ld.s b/llvm/test/MC/CSKY/tls_ld.s index c4cbf15..b0a026f 100644 --- a/llvm/test/MC/CSKY/tls_ld.s +++ b/llvm/test/MC/CSKY/tls_ld.s @@ -11,13 +11,13 @@ lrw16 r3, xxx@TLSLDO32 str32.w r4, (r0, r3 << 0) -# CHECK: 0: lrw16 r0, 0x18 <$d.0> +# CHECK: 0: lrw16 r0, 0x18 # CHECK-NEXT: 2: grs32 r2, 0x0 # CHECK-NEXT: 6: addu16 r0, r0, r2 -# CHECK-NEXT: 8: lrw16 r3, 0x1c <$d.0+0x4> +# CHECK-NEXT: 8: lrw16 r3, 0x1c # CHECK-NEXT: a: ldr32.w r3, (r28, r3 << 0) # CHECK-NEXT: e: jsr16 r3 -# CHECK-NEXT: 10: lrw16 r3, 0x20 <$d.0+0x8> +# CHECK-NEXT: 10: lrw16 r3, 0x20 # CHECK-NEXT: 12: str32.w r4, (r0, r3 << 0) # CHECK-NEXT: 16: bkpt diff --git a/llvm/test/MC/CSKY/tls_le.s b/llvm/test/MC/CSKY/tls_le.s index 3206643..6bf99d6 100644 --- a/llvm/test/MC/CSKY/tls_le.s +++ b/llvm/test/MC/CSKY/tls_le.s @@ -5,7 +5,7 @@ lsli32 r2, r31, 0 str32.w r0, (r2, r3 << 0) -# CHECK: 0: lrw16 r3, 0xc <$d.0> +# CHECK: 0: lrw16 r3, 0xc # CHECK-NEXT: 2: lsli32 r2, r31, 0 # CHECK-NEXT: 6: str32.w r0, (r2, r3 << 0) # CHECK-NEXT: a: bkpt